Decoupled Read Write Path Memory Cell Sneak Current Reduction
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Solution Overview
Problem
Resistive memory cells face issues with sneak currents, which adversely affect the sensing operation by causing unintended electric current flow through unselected memory cells, making it difficult to accurately determine the resistive state of targeted memory cells.
Innovation Solution
The implementation of a memory cell with a decoupled read/write path, where a switch and a resistive switching device are connected between a word line and a bit line, with a conductive path allowing current flow without passing through the switch terminals, reducing sneak currents by isolating the read and write paths and utilizing a sense amplifier to measure the resistive state based on the current flow through the resistive switching device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage is applied to conductive lines to read the state of a target memory cell, then the resistive state can be determined based on electric current, but sneak current flows through unselected memory cells and adversely affects the sensing operation
Solution Approach 1:
The memory cell is segmented into distinct read and write paths. The write path includes the resistive switching device connected between bit line and word line, while the read path includes a separate read transistor connected between bit line and source line. This segmentation allows independent optimization of read and write operations, preventing sneak current from affecting the read sensing operation while maintaining write functionality through the resistive switching device.
Solution Approach 2:
A read transistor is introduced as an intermediary component in the read path. This read transistor acts as a mediator that controls current flow during read operations, ensuring that current flows only through the selected memory cell's resistive switching device and not through unselected cells. The read transistor's gate is controlled by the word line, enabling selective activation and preventing sneak current paths.
2Measurement precision
If a conventional memory cell structure is used, then device complexity is reduced, but sneak current cannot be avoided and measurement precision deteriorates
Solution Approach 1:
The read transistor and resistive switching device are merged into a single memory cell structure, sharing common conductive lines (bit line and word line). The read transistor's gate is connected to the word line, and its drain is connected to the bit line, while the resistive switching device is connected between the bit line and word line. This merging allows the memory cell to perform both read and write operations within a unified structure, improving measurement precision without requiring completely separate read and write circuits.
Solution Approach 2:
The memory cell structure is designed with multi-functionality, where the same conductive lines (bit line and word line) serve both read and write operations. The read transistor can be activated for read operations while the resistive switching device remains intact for write operations. This universal structure eliminates the need for separate read and write paths with completely different components, reducing overall device complexity while maintaining improved measurement precision through the decoupled read path design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively minimizes sneak currents by ensuring the read path has a higher RC time constant, allowing for accurate determination of the resistive state without significant interference from sneak currents, thus improving the reliability of memory cell operations.
Implementation Method 1
Resistive memory systems use a resistive element that can change and maintain the value of its resistivity based on applied conditions. For example, a high resistive state may be used to represent a logical '1' while a low resistive state may be used to represent a logical '0'.
Implementation Method 2
A voltage may be applied to the appropriate conductive lines to read the state of a target memory cell. This voltage causes an electric current to flow through the target memory cell. Based on the value of this electric current, the resistive state of the memory cell can be determined.
Data Source
AI summary
A memory cell with a decoupled read/write path, the memory cell includes a switch comprising a gate, a first terminal and a second terminal, a resistive switching device connected to the gate of the switch, and a conductive path between the gate of the switch and the second terminal.