Serial-Gate Transistor Structure for Compact High-Voltage Memory
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Solution Overview
Problem
High-voltage transistors in semiconductor integrated circuits face challenges with peak electric fields, channel punch-through, and increased area requirements due to longer channels and thicker gate insulating films.
Innovation Solution
The introduction of a serial-gate transistor design with independently controlled gates and decoupled source-drain regions, reducing peak electric fields by distributing the electric field across multiple gates, thereby minimizing channel length and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating film thickness is increased to sustain high voltage, then the transistor can endure higher voltage, but the device area increases
Solution Approach 1:
The gate insulating film is divided into a first gate insulating film and a second gate insulating film with different dielectric constants. The first gate insulating film (closer to the channel) has higher dielectric constant than the second gate insulating film (farther from the channel). This segmentation allows the structure to sustain high voltage while maintaining a thinner overall film thickness, thereby reducing device area while preserving voltage endurance.
2Reliability
If the channel length is increased to endure electric field, then the transistor can sustain high voltage, but the device area increases
Solution Approach 1:
The channel structure is modified by introducing a third doped region adjacent to the drain region, creating a gradient in doping concentration along the channel. This local quality change allows the channel to endure high electric fields without requiring a longer overall channel length, thus reducing device area while maintaining electric field endurance.
3Reliability
If the channel length is increased to prevent punch-through, then the transistor can sustain high voltage, but the device area increases
Solution Approach 1:
A third doped region is introduced adjacent to the drain region with doping concentration between that of the source and drain regions. This creates a gradual doping profile that prevents abrupt potential changes, effectively preventing punch-through phenomenon without requiring increased channel length, thereby maintaining compact device area.
Data Source
AI summary
The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.