Decoupling Capacitor Circuit Assembly for PCB Area Conservation
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Solution Overview
Problem
The physical size of discrete decoupling capacitors on printed circuit boards (PCBs) around integrated circuits (ICs) occupies valuable real estate, hindering the quality of routing conductive traces and signal quality.
Innovation Solution
A decoupling capacitor circuit assembly that includes a passive substrate with terminals on its top surface and capacitors mounted to its bottom surface, which are coupled to the PCB lands, reducing the need for additional space on the PCB by integrating decoupling capacitance for the IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete decoupling capacitors are mounted on the PCB around the IC, then decoupling capacitance is provided to reduce noise and prevent voltage sag, but valuable PCB real estate is occupied and signal routing quality deteriorates
Solution Approach 1:
The patent combines the decoupling capacitor mounting surface with the PCB substrate by integrating capacitive elements directly into the PCB layers. This merging eliminates the need for separate discrete capacitor components and their associated mounting space, while maintaining the decoupling function. The capacitive elements are formed as integrated structures within the PCB, combining the substrate and capacitor functions into a single unified component.
Solution Approach 2:
The patent transitions from two-dimensional surface mounting of discrete capacitors to three-dimensional integrated structures within the PCB layers. By forming capacitive elements that extend through multiple PCB layers and utilizing vertical space within the substrate, the solution provides decoupling capacitance without occupying additional horizontal PCB real estate, effectively moving the solution into the vertical dimension.
2Reliability
If discrete decoupling capacitors are mounted on the PCB, then decoupling capacitance is provided, but the quality of routing conductive traces and signal quality deteriorates
Solution Approach 1:
The patent merges the decoupling function with the PCB signal routing structure by integrating capacitive elements directly into the signal path layers. This integration allows for optimized trace routing without the need to navigate around discrete capacitor components, improving signal quality and routing efficiency while maintaining power system stability.
3Reliability
If more decoupling capacitors are added to provide sufficient capacitance, then power noise reduction improves, but PCB area consumption increases
Solution Approach 1:
The patent provides sufficient decoupling capacitance by utilizing the vertical dimension through multi-layer PCB structures. Capacitive elements are formed across multiple internal layers, allowing the accumulation of sufficient capacitance value without increasing the horizontal footprint. This dimensional transition enables adequate noise reduction while conserving PCB real estate.
Solution Approach 2:
The patent employs composite PCB structures with multiple dielectric layers and conductive patterns that collectively provide the required decoupling capacitance. By using composite material structures with different dielectric properties arranged in specific configurations, sufficient capacitance is achieved within a compact footprint, reducing PCB area consumption while maintaining noise reduction effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution conserves PCB area, potentially reducing manufacturing costs and improving signal routing quality by providing decoupling capacitance without increasing the PCB's vertical height.
Implementation Method 1
The at least one capacitor is mounted to the bottom surface of the passive substrate and is configured to provide decoupling capacitance for an integrated circuit (IC) on the PCB
Data Source
AI summary
Decoupling capacitor circuit assembly is described. In one example, a circuit assembly includes a passive substrate, a plurality of terminals, and at least one capacitor. The passive substrate includes a top surface and a bottom surface. The plurality of terminals is formed on the top surface and is configured for electrical communication with a respective plurality of lands on a printed circuit board (PCB). The at least one capacitor is mounted to the bottom surface of the passive substrate and is configured to provide decoupling capacitance for an integrated circuit (IC) on the PCB. Each capacitor is coupled to a pair of the plurality of terminals. In another example, a circuit assembly includes a PCB, and IC mounted to the PCB, a passive substrate mounted to the PCB, and at least one capacitor mounted to the passive substrate for providing decoupling capacitance for the IC.