Decoupling Capacitor Using Complementary NFET PFET Transistors
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Solution Overview
Problem
Existing decoupling capacitors in semiconductor circuits have poor decoupling capacitance characteristics and low capacitance density, particularly at high frequencies, due to large channel resistance and area inefficiency, and well jogging increases well proximity effects and reduces capacitance density.
Innovation Solution
A decoupling capacitor design using an NFET and a PFET transistor, where the transistors are arranged with straight boundaries between n-type and p-type portions, allowing for high capacitance density and area efficiency, and can be integrated into standard cell blocks without well jogging, reducing leakage current and improving frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a single FET decoupling capacitance is used with minimum channel separation, then area is reduced, but channel resistance becomes too large to respond to high frequency variations
Solution Approach 1:
The decoupling capacitor is segmented into two separate FET devices (first FET and second FET) with opposite polarity types. This segmentation allows each device to have optimized channel dimensions for low resistance while maintaining compact overall area through complementary layout arrangements.
Solution Approach 2:
The patent employs asymmetric device sizing where the first FET and second FET can have different width-to-length ratios tailored to their specific polarity requirements. This allows optimization of channel resistance for high-frequency response while maintaining area efficiency through complementary placement.
2Quantity of substance
If channel lengths are increased to improve capacitance density, then capacitance density increases, but response time becomes rapidly poorer
Solution Approach 1:
The patent optimizes the width-to-length ratios of the FET channels as key parameters. By carefully selecting these dimensions, the design achieves high capacitance density through increased width while maintaining short channel length to ensure rapid response time for high-frequency variations.
Solution Approach 2:
The decoupling capacitor uses FET devices with channel dimensions that provide excessive capacitance density beyond minimum requirements, while keeping channel lengths at minimum values to ensure response time is not compromised. The complementary polarity devices work together to provide sufficient decoupling capability.
3Area of moving object
If well jogging is used to increase decoupling capacitance area, then capacitance area increases, but well proximity effects on adjacent cells increase and capacitance density decreases
Solution Approach 1:
The patent uses a composite structure combining n-type and p-type FET devices in a complementary configuration. This composite approach allows the decoupling capacitance to be formed using both polarity devices sharing a common active region, eliminating the need for well jogging and reducing well proximity effects on adjacent cells.
Solution Approach 2:
The first FET and second FET with opposite polarities are merged into a shared active region structure. This merging allows both devices to utilize the same substrate area without requiring well jogging, thereby reducing well proximity effects while maintaining high capacitance density through efficient space utilization.
4Area of moving object
If minimum channel length is used to reduce area, then area efficiency improves, but channel resistance becomes too large to be useful
Solution Approach 1:
The decoupling function is segmented into two complementary FET devices that share the active region. This segmentation allows each device to contribute to the overall decoupling capacitance with optimized channel dimensions, achieving low effective resistance while maintaining compact area through complementary polarity placement.
Solution Approach 2:
The complementary pair of n-type and p-type FETs forms a composite decoupling structure where the combined effect of both devices provides sufficient decoupling capacitance with low effective resistance. The composite structure utilizes shared active regions to achieve area efficiency without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high capacitance density and improved frequency response by eliminating well jogging and optimizing transistor placement, enabling effective compensation for high-frequency power fluctuations without increasing circuit area, and reducing leakage current.
Implementation Method 1
the gate capacitance of the PFET is connected to the low power rail VSS through the channel of the NFET and the NFET gate capacitance is connected to the VDD node through the channel of the PFET
Data Source
AI summary
A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor. The decoupling capacitor is formed of an NFET transistor and a PFET transistor, the PFET transistor being substantially formed in the n-type portion and the NFET transistor being substantially formed in the p-type portion, a boundary between the n-type portion and the p-type portion being substantially straight. The transistors are arranged such that a source and drain of the PFET transistor are connected to a high voltage rail and a source and drain of the NFET transistor are connected to a low voltage rail.