Real-Time Decoupling Capacitor Placement Examination
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Solution Overview
Problem
Current printed board design methods require completing the entire arrangement/wiring design before examining power supply noise, leading to long turn-around times and inability to perform real-time checks for adequate decoupling capacitor placement during the design phase.
Innovation Solution
A printed board design system that includes a decoupling capacitor pin position information obtain unit, power supply plane position/shape information obtain unit, restriction information input unit, and decoupling capacitor examination unit, allowing for real-time judgment on the adequacy of decoupling capacitor placement on the power supply plane during the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power supply noise examination is performed after completing entire arrangement/wiring design, then examination accuracy is improved, but design time is significantly increased
Solution Approach 1:
The patent applies preliminary action by performing power supply noise examination during the arrangement/wiring design phase rather than after completion. The examination unit calculates power supply noise in real-time as the design is being created, enabling early detection of issues and allowing designers to correct problems before finalizing the entire board layout, thus reducing overall design time while maintaining examination accuracy.
2Productivity
If decoupling capacitor placement is examined in real-time during design, then design efficiency is improved, but examination complexity increases
Solution Approach 1:
The patent applies self-service by enabling the design system to automatically perform power supply noise examination and decoupling capacitor placement verification without requiring manual intervention or complex external tools. The examination unit integrates directly into the design software, automatically calculating noise levels and identifying inadequate capacitor placements based on pre-defined criteria, thereby improving design efficiency while managing complexity through automation.
3Device complexity
If decoupling capacitor placement is not examined until design completion, then design process is simpler, but power supply noise control is compromised
Solution Approach 1:
The patent applies feedback by implementing real-time examination of decoupling capacitor placement during the design process. The examination unit continuously monitors the design state, calculates power supply noise levels, and provides immediate feedback on whether capacitor placements are adequate. This feedback mechanism allows designers to adjust their arrangements dynamically, ensuring proper power supply noise control while maintaining a relatively simple design process through automated guidance.
Data Source
AI summary
A decoupling capacitor pin position information obtain unit calculates based on board design data of a printed board, position information indicating positions of decoupling capacitors on the printed board. A power supply plane position/shape information obtain unit calculates based on the board design data, position/shape information indicating a position and shape of a power supply plane of the printed board. A restriction condition input unit collects restriction conditions from an input device. A decoupling capacitor examination unit judges based on the position information, the position/shape information and the restriction conditions, whether or not arrangement of the decoupling capacitors is adequate. Therefore, a designer, while designing arrangement/wiring of the printed board, can check in real time whether or not the arrangement of the decoupling capacitors is adequate, and thus can design at higher speed a printed board in which arrangement of decoupling capacitors is adequate.