Decoupling Capacitor Layout Under Power Wiring for Low-Height IC Cells
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Solution Overview
Problem
Conventional semiconductor integrated circuit devices face malfunctions due to power supply noises, particularly with reduced cell height leading to insufficient decoupling capacity and weakened noise resistance, as the narrower transistor width and reduced space between gates result in decreased capacitance.
Innovation Solution
The layout of a semiconductor integrated circuit device includes a first power supply wiring with a capacitive element formed under it, extending across the second and third power supply wirings, allowing for a greater transistor gate width and maintaining sufficient capacitance even with reduced cell height, thereby enhancing noise resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the cell height is lowered to reduce chip area, then the chip area is reduced, but the transistor width and space between gates are reduced, resulting in decreased capacitance and weakened noise resistance
Solution Approach 1:
The patent places the capacitive element under the power supply wiring in the vertical dimension rather than between power supply wirings in the horizontal dimension. This allows the transistor gate to extend in the vertical direction beneath the power supply wiring, effectively utilizing the third dimension (depth) to increase gate width and capacitance without increasing the horizontal cell footprint, thus maintaining noise resistance while reducing chip area.
Solution Approach 2:
The capacitive element is nested under the power supply wiring structure, with the transistor gate positioned vertically beneath the power supply wiring. This nesting arrangement allows the capacitive element to occupy the space under the existing power supply wiring, maximizing space utilization and maintaining sufficient capacitance within the reduced cell height constraint.
2Reliability
If both NMOS and PMOS transistors are used to form capacitive elements for effective voltage variation control, then noise resistance is improved, but the cell height must be increased to accommodate both transistors with sufficient gate widths
Solution Approach 1:
The patent utilizes the vertical dimension by placing the capacitive element under the power supply wiring, allowing the transistor gate to extend downward beneath the wiring. This vertical extension provides sufficient gate width for achieving high capacitance without increasing the horizontal cell dimensions, thereby maintaining noise resistance while avoiding increased cell height.
3Reliability
If the transistor gate width is increased to maintain sufficient capacitance, then the decoupling capacity is improved, but the cell height must be increased to accommodate the larger gate width
Solution Approach 1:
The patent resolves this contradiction by extending the transistor gate in the vertical dimension beneath the power supply wiring. This allows the gate width to be sufficiently large for high capacitance and decoupling capacity without requiring increased horizontal cell dimensions, thereby maintaining decoupling capacity while avoiding increased cell height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces power-supply noises and maintains sufficient capacitance, improving the performance of the semiconductor integrated circuit device by allowing for greater transistor width and enhanced noise resistance.
Implementation Method 1
a gate electrode as a first polarity, a channel as a second polarity formed on a semiconductor substrate under the gate electrode, whereby the transistor works as a capacitive element
Data Source
AI summary
A layout for a semiconductor integrated circuit device can maintain a sufficient capacitance of a capacity cell even when a height of the cell is lowered. In this layout, power supply wiring extending along a first direction supplies a first supply voltage, power supply wiring and power supply wiring extending in parallel with the power-supply wiring supply a second and a third supply voltages respectively. Capacitive element is formed of a transistor that receives the first supply voltage at its source and drain, and receives the second or the third supply voltages at its gate. Capacitive element is disposed under power supply wiring such that it strides over a portion at power supply wiring side and a portion at power supply wiring side.