Decoupling Composite Capacitor in Semiconductor Wafer
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Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) and Metal Oxide Semiconductor (MOS) capacitors used for decoupling in semiconductor wafers consume significant die space, reducing the available space for other circuit elements.
Innovation Solution
A method for fabricating a decoupling composite capacitor in a wafer, involving the formation of through-wafer via openings, insulators, and conductors, along with metal segments and a redistribution layer, to create a capacitor structure that utilizes the backside of the die for minimal area consumption while providing high capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MIM capacitors or MOS capacitors are used for decoupling, then decoupling function is provided, but die space is significantly reduced
Solution Approach 1:
The patent transitions from planar capacitor structures to a three-dimensional configuration by forming a through-wafer via that extends vertically through the substrate. This vertical dimension allows the capacitor to achieve high capacitance without occupying excessive lateral die space, resolving the contradiction between decoupling function and space consumption
2Reliability
If conventional decoupling capacitors are fabricated, then electrical noise reduction is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent combines the decoupling capacitor fabrication with the existing through-wafer via formation process. By integrating the capacitor structure into the via structure and using the same deposition and etching steps, the manufacturing complexity is reduced while still achieving effective electrical noise reduction
Data Source
AI summary
According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.