Decoupling Deselected Word-lines for Accurate Memory Cell Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The ripple present on the bias voltage of deselected word-lines during verify read operations can cause distortion of the voltage ramp applied to addressed array cells, leading to incorrect cell state verification and potential over-erasing or under-programming, especially in multi-level FLASH memory devices, due to coupling capacitances and voltage ripple from charge pump generators.
Innovation Solution
Temporarily decoupling deselected word-lines from the bias voltage distribution network during the voltage ramp applied to the control gate of addressed and reference cells by placing them in a high impedance state or stopping the charge pump generator, thereby isolating the voltage divider and preventing perturbations in the bias voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deselected word-lines are connected to bias voltage distribution network during verify read operations, then the bias voltage can be continuously supplied to maintain operational readiness, but voltage ripple from charge pump generators causes distortion of the voltage ramp applied to addressed array cells
Solution Approach 1:
The patent extracts the deselected word-lines from the bias voltage distribution network during verify read operations by placing them in high impedance state. This isolation removes the source of voltage ripple distortion caused by charge pump generators, preventing the ripple from coupling into the voltage ramp applied to addressed array cells through coupling capacitances.
Solution Approach 2:
The patent applies preliminary action by temporarily disconnecting deselected word-lines from the bias voltage distribution network before the voltage ramp is applied during verify read operations. This preventive measure eliminates the possibility of voltage ripple distortion before it can occur, ensuring accurate cell state verification.
2Reliability
If deselected word-lines are placed in high impedance state during verify read operations, then voltage ripple disturbances are eliminated, but the bias voltage distribution network requires additional control mechanisms
Solution Approach 1:
The patent applies dynamics by making the connection of deselected word-lines to the bias voltage distribution network temporary and variable. The word-lines are dynamically switched to high impedance state during verify read operations and then restored to normal operation afterward. This dynamic control is achieved through timing signals that coordinate with the verify read operation cycle.
3Reliability
If charge pump generator is stopped during voltage ramp application, then voltage ripple is eliminated, but the bias voltage supply is interrupted
Solution Approach 1:
The patent extracts the harmful voltage ripple from the system by isolating deselected word-lines from the bias voltage distribution network during verify read operations, rather than stopping the charge pump generator entirely. This approach eliminates the ripple disturbance while maintaining continuous bias voltage supply to the memory array.
Solution Approach 2:
The patent introduces an intermediary mechanism (high impedance state switching) between the charge pump generator and the deselected word-lines. This intermediary allows the charge pump to continue operating and supplying bias voltage while preventing the voltage ripple from coupling into the active verify read operation through the deselected word-lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates disturbances caused by voltage ripple, ensuring accurate cell state verification and recovery during erase and program operations, reducing the risk of over-erasing or under-programming and maintaining the stability of the bias voltage level.
Implementation Method 1
due to coupling capacitances and voltage ripple from charge pump generators
Data Source
AI summary
A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.