Decoy Via Gettering Vacancies to Protect Functional Vias
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Solution Overview
Problem
Semiconductor devices with vias on tabs face high failure probabilities due to stress-induced voiding, and existing solutions lack effective redundancy options, especially when space is limited.
Innovation Solution
A semiconductor device design incorporating a decoy via aligned in a protection region between different interconnect layers to getter vacancies and protect the functional via from failure, with the decoy via connected between a metal portion of the first interconnect layer and a metal portion of a third interconnect layer, providing additional protection without compromising the functional via's integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via is placed on a tab to reduce stress-induced voiding, then the via's susceptibility to failure decreases, but the available options for redundant vias are limited
Solution Approach 1:
The patent introduces a decoy via in a different interconnect layer (third layer) than the functional via (second layer), utilizing the vertical dimension to provide redundancy. This dimensional approach allows the decoy via to be positioned in a protection region without conflicting with the tab geometry constraints, thereby providing redundancy options while maintaining via reliability.
2Reliability
If the bus width is increased to reduce resistance, then the current carrying capacity improves, but the risk of stress-induced voiding at the vias increases
Solution Approach 1:
The decoy via acts as an intermediary element that absorbs or redirects stress-induced vacancies away from the functional via. By positioning the decoy via in the protection region, it serves as a sacrificial element that mitigates the harmful stress effects on the functional via, allowing the bus to maintain increased width for better current carrying capacity without proportionally increasing via failure risk.
3Reliability
If redundant vias are provided to compensate for via failures, then the device's reliability improves, but the device complexity increases
Solution Approach 1:
The decoy via serves multiple functions: it provides redundancy for the functional via, acts as a stress relief element to redirect vacancies, and is integrated into the existing interconnect layer structure. This multi-functionality allows the system to achieve improved reliability without proportionally increasing complexity, as the decoy via leverages existing manufacturing processes and structural elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The decoy via effectively redirects vacancies away from the functional via, reducing the likelihood of failure and maintaining the semiconductor device's integrity by being positioned in a non-functional path, thus enhancing the reliability of the device.
Implementation Method 1
the decoy via provides gettering of vacancies and thus protects the via that is susceptible to failure when vacancies are coming from the first interconnect layer
Data Source
AI summary
A method is for forming a decoy via and a functional via. The method includes forming the functional via between a metal portion of a first interconnect layer and a portion of a second interconnect layer. The method further includes forming the decoy via in a protection region between the metal portion of the first interconnect layer and a metal portion of the third interconnect level.