Decryption Hardware Circuit for On-the-fly Data Security
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Solution Overview
Problem
Current microprocessor systems face performance penalties due to the need for decryption of encrypted data, which requires complex and latency-introducing mask generation, and existing memory controllers are not designed to handle decryption, compromising their maturity and efficiency.
Innovation Solution
An external decryption hardware circuit is implemented that generates decryption masks in advance using a speculative procedure, allowing for on-the-fly decryption of data without adding latency, and is configured to protect AES keys and vectors from hacking through a secure path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored encrypted in non-volatile memory to protect against reverse engineering, then security is improved, but decryption adds penalties to microprocessor performance
Solution Approach 1:
The decryption function is extracted from the microprocessor and implemented as a separate hardware circuit. This dedicated decryption circuit handles mask generation and decryption operations independently, preventing these operations from consuming microprocessor cycles and thus eliminating the performance penalty while maintaining security protection.
Solution Approach 2:
A dedicated decryption circuit acts as an intermediary between the encrypted data in non-volatile memory and the microprocessor. This intermediate hardware component performs decryption operations using pre-generated masks, allowing the microprocessor to access decrypted data without directly performing decryption computations.
2Speed
If a dedicated hardware circuit is used to generate AES decryption masks to minimize mask generation time, then decryption speed is improved, but device complexity increases
Solution Approach 1:
Decryption masks are generated in advance during system initialization or boot-up phase and stored in dedicated hardware registers. This preliminary generation of masks eliminates the need for complex real-time mask generation during decryption operations, reducing both the complexity of the decryption circuit and the time required for actual decryption.
Solution Approach 2:
The system changes the state of decryption masks from dynamically generated to pre-computed static values. By transforming masks from runtime-generated parameters to pre-established constants, the hardware complexity is reduced while maintaining high decryption speed through simple lookup and application of pre-generated masks.
3Adaptability or versatility
If memory controller is redesigned to support decryption operations, then decryption capability is improved, but manufacturing maturity is compromised
Solution Approach 1:
The decryption functionality is extracted from the memory controller and implemented as a separate dedicated circuit. This allows the memory controller to remain unchanged and maintain its manufacturing maturity, while the extracted decryption circuit provides the necessary decryption capability independently.
Solution Approach 2:
The system is segmented into distinct functional modules: the original memory controller handles memory access operations, while a separate decryption module handles decryption operations. This segmentation allows each component to be optimized independently, preserving the manufacturing maturity of the memory controller while adding decryption capability through a dedicated module.
Data Source
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AI summary
An electronic device is described, comprising a digital module (11; 21; 31; 41) comprising a module, in particular a microprocessor, to access a non volatile memory (12), an internal memory (13), in particular a RAM, and a non volatile memory (16), in particular a flash memory, for storing data from the non-volatile memory (16), said data (CB) being stored encrypted in said non volatile memory. Said digital module includes a decryption module (22) configured to perform a decryption on the fly of blocks of data read from said non volatile memory stored encrypted in said non volatile memory to obtain read decrypted data (RB), said decryption module being arranged interposed on a interconnect network (14) identifying a data path for exchanging data (RB, WB) between said non-volatile memory and said module to access a non volatile memory.