Dedicated DFT Paths for Memory Sub-System Controller
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Solution Overview
Problem
Conventional memory sub-system controller designs face challenges in test and debug accessibility due to incomplete register mapping, wire congestion, and non-native access to functional component DFT registers, which complicates verification and increases signal routing and chip area.
Innovation Solution
The implementation of dedicated DFT paths using custom serial interface components, such as a two-wire connection to a serial interface component like an I2C bus, allows for native access to functional component DFT functionality, reducing wire count and standardizing interfaces through protocol conversion between parallel and serial communication protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional register mapping methods are used to access functional component DFT registers, then access to test and debug interfaces is possible, but wire congestion increases and chip area expands
Solution Approach 1:
The patent introduces a dedicated DFT path as an intermediary mechanism that provides native access to functional component DFT registers. This dedicated path acts as a mediator between the testing subsystem and the DFT registers, eliminating the need for extensive wire routing through the main bus structure. The dedicated path includes specialized circuitry that directly interfaces with DFT registers, thereby reducing wire congestion and chip area while maintaining ease of access for test and debug operations.
2Ease of operation
If conventional register mapping is used, then test interfaces can be accessed, but wire congestion occurs
Solution Approach 1:
The patent segments the access path to DFT registers by creating a dedicated DFT path that is separate from the main bus structure. This segmentation isolates the test and debug access functionality from the primary data and control signal routing, thereby reducing wire congestion in the main system. The dedicated path includes its own specialized wires and circuitry that directly connect to functional component DFT registers without interfering with normal operation signals.
3Ease of operation
If native access to functional component DFT registers is implemented, then test and debug operations are simplified, but additional circuitry is required
Solution Approach 1:
The dedicated DFT path is designed with multi-functionality to minimize additional circuitry. The path can serve multiple functional components through time-multiplexed access, where a single dedicated DFT interface can sequentially access DFT registers across different functional blocks. This universal approach reduces the need for separate dedicated circuitry for each functional component, thereby simplifying the overall circuit structure while maintaining native access capabilities for test and debug operations.
Data Source
AI summary
Command execution data is received. The command execution data comprises a block address corresponding to an functional component, a register identifier corresponding to a design for testability (DFT) register of the functional component, and command data. The command execution data is converted to a serial command. The serial command is committed to the DFT register of the functional component. A response to the serial command is received. The response is generated by the functional component based on the serial command. The response is converted to command response data and is provided to a testing sub-system.