Dedicated ECC Circuit Layout for Low-Latency Redundancy Input
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Solution Overview
Problem
The existing memory devices face increased latency in error correction operations due to the lengthy data path required to transfer redundant data bits to error correction circuitry, which can delay retrieval operations.
Innovation Solution
Implementing a direct-input redundancy scheme with a dedicated error correction code (ECC) circuit that reduces the data path length by directly inputting redundancy data bits into an ECC circuit dedicated to the redundant data plane, coupled with adaptive enablement circuitry and syndrome decoders to manage inputs effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant data bits are transferred through the existing data path to error correction circuitry, then error correction can be performed, but propagation delay increases and retrieval operation latency increases
Solution Approach 1:
The error correction system is segmented into multiple dedicated ECC circuits, each responsible for specific data planes. Redundant data bits are directly input to the dedicated ECC circuit corresponding to their source data plane, eliminating the need to traverse the entire data path through a single centralized error correction unit. This segmentation parallelizes the error correction process and reduces propagation delay.
Solution Approach 2:
Dedicated ECC circuits act as intermediaries between the redundant data bits stored in specific data planes and the syndrome decoding logic. Each dedicated ECC circuit receives redundant data bits directly from its associated data plane and performs error correction locally, serving as an intermediary that eliminates the need for long-distance data traversal through shared pathways.
2Device complexity
If a single error correction circuit processes all data planes, then device complexity is reduced, but data path length increases causing delay
Solution Approach 1:
The error correction functionality is divided into multiple dedicated ECC circuits, each handling specific data planes. This segmentation increases the number of circuit components but dramatically reduces the data path length for each circuit, as each dedicated ECC circuit receives data directly from its associated data plane without traversing through other data planes' pathways.
Solution Approach 2:
Each dedicated ECC circuit is optimized for its specific data plane, with data paths and circuitry localized to that plane. This local quality ensures that error correction for each data plane occurs with minimal propagation delay, as the data path length is optimized for local processing rather than global traversal.
3Reliability
If redundant data bits traverse through multiple data planes to reach error correction circuitry, then error correction is achieved, but propagation delay increases
Solution Approach 1:
The system segments error correction processing into dedicated circuits for each data plane, allowing redundant data bits to be processed in parallel rather than sequentially traversing through multiple data planes. This segmentation maintains data integrity through proper error correction while significantly improving error correction speed by eliminating multi-plane traversal delays.
Solution Approach 2:
Dedicated ECC circuits are pre-configured and ready to receive redundant data bits directly from their associated data planes. This preliminary preparation of dedicated error correction pathways ensures that when data needs correction, the process can begin immediately without the delay of routing data through multiple intermediate data planes.
Data Source
AI summary
Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.