Dedicated Function Pin Reuse for FPGA Multi-Site Testing
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Solution Overview
Problem
The limited availability of dedicated function pins in Automated Test Equipment (ATE) multi-site testing platforms constrains the number of test sites for simultaneous testing of FPGAs, thereby reducing test throughput.
Innovation Solution
Implementing a system where dedicated function pins, such as JTAG pins, are used in a non-dedicated function test mode by controlling a state-storing device to select between processing and deactivating the circuit block, allowing these pins to be used for testing the FPGA fabric, thereby increasing test throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated function pins are used exclusively for dedicated function testing, then dedicated function testing is performed reliably, but the number of available test sites is reduced and test throughput is constrained
Solution Approach 1:
The patent enables dedicated function pins to serve dual purposes: they can be used for their original dedicated function testing (such as JTAG boundary scan) or repurposed for non-dedicated function testing of FPGA fabric. This multi-functionality is achieved through control logic that routes signals from dedicated function pins to either the dedicated function circuitry or to the FPGA fabric test mode, thereby increasing the number of available test sites without sacrificing dedicated function testing capability.
2Productivity
If dedicated function pins are allocated for ATE multi-site testing platform, then simultaneous testing of multiple FPGAs is enabled, but pin constraints are increased and test sites are limited
Solution Approach 1:
The patent resolves pin constraints by making dedicated function pins universal resources that can be dynamically allocated. The control logic allows these pins to be shared between dedicated function testing and FPGA fabric testing, effectively increasing the available pin bandwidth for multi-site testing without adding more physical pins to the ATE platform.
Solution Approach 2:
The patent introduces dynamic control logic that can switch the function of dedicated function pins based on test requirements. The state-storing device and control logic enable runtime reconfiguration of pin functionality, allowing the system to adapt pin allocation dynamically rather than being statically constrained, thereby supporting more simultaneous test sites.
3Productivity
If non-dedicated function pins are used for testing FPGA fabric, then test pattern signaling is provided, but the number of available pins is limited and throughput is constrained
Solution Approach 1:
The patent increases the quantity of pins available for FPGA fabric testing by enabling dedicated function pins to also perform non-dedicated function testing. The control logic routes test pattern signals to the FPGA fabric through dedicated function pins when in non-dedicated test mode, effectively doubling the pool of pins available for fabric testing beyond just the non-dedicated function pins.
Data Source
AI summary
Testing an integrated circuit using dedicated function pins in a non-dedicated function test mode is described. In a first mode, a circuit block is activated for processing first information provided via dedicated function pins. In a second mode, the circuit block is deactivated. Control logic is coupled to receive state information from a state storing device and coupled to receive the first information and second information from the dedicated function pins. The control logic is configured to gate the second information for passage to programmable logic responsive to the state information being for the second mode. The control logic is configured to gate the first information to preclude passage to the programmable logic responsive to the state information being for the first mode.