Dedicated Interrupt Core for Multi-Core Processor Speed
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Solution Overview
Problem
Conventional interrupt handling in multi-core processors often prolongs operation time and lowers speed due to suspension of normal operations and potential cache rewriting, and existing solutions relying on OS assignment are not practical for server vendors without OS development capabilities.
Innovation Solution
A processor configuration with a dedicated interrupt operation core and a normal core that assigns interrupt operations via an interrupt control part, allowing direct assignment of interrupt vectors to the dedicated core without OS intervention, thereby bypassing OS-dependent assignment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupt operation is performed by suspending normal operation in a single core, then interrupt handling can be executed, but operation time is prolonged and operation speed is lowered
Solution Approach 1:
The processor is divided into two distinct cores: a normal operation core for executing regular programs and an interrupt operation dedicated core for handling interrupt requests. This segmentation allows interrupt handling to occur independently without suspending normal operations, thereby maintaining operation speed while ensuring reliable interrupt processing.
Solution Approach 2:
The interrupt handling function is extracted from the normal operation core and assigned to a dedicated interrupt operation core. This extraction eliminates the need to suspend normal operations for interrupt processing, preventing operation time prolongation and speed reduction while maintaining complete interrupt handling capability.
2Reliability
If interrupt operation is performed by suspending normal operation, then interrupt handler can be executed, but cache contents may be rewritten causing operation speed to be lowered after normal operation is restored
Solution Approach 1:
By segmenting the processor into separate normal operation core and interrupt operation dedicated core, the patent ensures that interrupt operations execute in isolation without affecting the cache state of normal operations. This prevents cache content rewriting and the associated time loss when restoring normal operations.
3Adaptability or versatility
If OS assignment is used for interrupt operation CPU, then interrupt CPU can be assigned according to interrupt source, but it is not practical for server vendors without OS development capabilities
Solution Approach 1:
The interrupt control part within the processor automatically performs interrupt CPU assignment based on interrupt vectors without requiring OS intervention. This self-service mechanism provides adaptability for different interrupt sources while eliminating the need for OS development, making the system practical for server vendors.
Solution Approach 2:
The interrupt control part acts as an intermediary between the interrupt source and the interrupt operation dedicated core, automatically managing the assignment process. This intermediary function provides the flexibility of OS-based assignment while removing the dependency on OS software, enabling easy implementation for server vendors.
Data Source
AI summary
A processor 1 provided with a plurality of cores, an interrupt operation dedicated core 20 which is used only for an interrupt operation; a normal core 11 to 1n which outputs an interrupt request when an interrupt source is generated; and an interrupt control part 30 which, upon receipt of the interrupt request, assigns an operation by an interrupt vector to the interrupt operation dedicated core 20.