Dedicated Register Pairs for Thread Command Processing

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Solution Overview

Problem

Existing embedded systems with shared registers for multiple threads incur significant processing overhead due to thread synchronization and state checking, leading to increased processing time and resource utilization.

Innovation Solution

Implementing a hardware acceleration block with dedicated pairs of registers (submission and completion registers) for each thread, eliminating the need for mutual exclusion checks and state indicator readings, and using a predetermined time gap between commands to prevent timing violations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If shared registers are used for multiple threads, then device complexity is reduced, but processing overhead increases due to thread synchronization and state checking

Engineering Contradiction:

Improveregister structureVSAvoidprocessing throughput

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent divides the shared register structure into dedicated register pairs for each thread. Each thread gets its own submission register and completion register, eliminating the need for threads to share registers and reducing synchronization overhead. This segmentation resolves the contradiction by accepting increased device complexity (more registers) to achieve higher productivity (faster processing).

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a timing mechanism as an intermediary between thread command submission and processing. By requiring threads to wait for a predetermined time gap between commands, the system mediates access to the hardware acceleration block without requiring complex synchronization logic in the register management, reducing processing overhead while maintaining dedicated register assignments.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If thread synchronization and state checking are implemented, then reliability is improved, but processing time increases

Engineering Contradiction:

Improvethread management correctnessVSAvoidprocessing delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by requiring threads to wait for a predetermined time gap before submitting the next command. This advance timing constraint eliminates the need for runtime state checking and synchronization waits, ensuring reliability through pre-established timing rules while reducing processing time by removing runtime overhead.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Each thread manages its own timing and command submission节奏 independently using its dedicated registers and the predetermined time gap rule. Threads self-regulate their command submission without requiring external synchronization control from the hardware acceleration block, improving reliability through decentralized control while reducing processing delays.

Inventive Principle:

Principle #25Self-service

3Speed

If dedicated register pairs are assigned to each thread, then processing speed is improved, but device complexity increases

Engineering Contradiction:

Improvethread processing speedVSAvoidregister configuration

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the register file into multiple dedicated pairs, with each pair assigned to a specific thread. This segmentation enables parallel command submission and completion tracking for multiple threads simultaneously, improving processing speed. The increased device complexity is justified by the elimination of synchronization overhead and enablement of true parallel processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each thread receives customized local quality through its dedicated register pair, optimized for its specific processing needs. The submission register and completion register are locally assigned to each thread, eliminating cross-thread interference and enabling optimized processing paths for each thread while accepting the overall system complexity increase.

Inventive Principle:

Principle #3Local quality

4Reliability

If state indicator checks are performed, then timing violations are prevented, but resource utilization decreases

Engineering Contradiction:

Improvetiming violation preventionVSAvoidresource utilization

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent establishes the predetermined time gap rule as a preliminary constraint before command submission. This advance timing rule prevents timing violations by ensuring adequate processing time for each command before the next submission, eliminating the need for runtime state indicator checks and improving resource utilization by removing the overhead of compliance verification.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10210032B2Processing commands via dedicated register pairs for each thread of a plurality of threads

Publication Date: 2019.02.19 INTEL CORP

AI summary

A hardware acceleration block is configured to process via a dedicated pair of registers, a plurality of commands of each of a plurality of threads received from a compute complex. The hardware acceleration block receives successive commands that are separated by at least an amount of time, from a thread of the plurality of threads. The amount of time is adequate to process a command from the thread.