Dedicated Serial Bus Topology for Memory Module Signal Balance
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Solution Overview
Problem
Conventional memory devices face imbalanced loading of control/address and clock lines compared to data lines, leading to inefficiencies in signal transmission and increased complexity in circuit board wiring.
Innovation Solution
Implementing dedicated pairs of serial data and control busses with the same net topology to directly couple memory devices to a memory controller, ensuring balanced loading and simplified connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional shared C/A bus and clock bus are used to connect multiple memory devices to the memory controller, then the number of signal lines is reduced, but the loading on control/address and clock lines becomes unbalanced compared to data lines
Solution Approach 1:
The patent divides the shared control/address bus into dedicated control busses for each memory device set. Instead of one shared C/A bus serving all memory devices, separate control busses are provided for each set of memory devices, allowing independent control and balanced loading characteristics similar to dedicated data busses.
Solution Approach 2:
The patent implements different bus configurations for different parts of the memory system. Each memory device set has its own dedicated control bus with specific loading characteristics matched to its data bus, rather than using a uniform shared bus configuration for all devices.
2Ease of operation
If buffered solutions (RDIMM, FBDIMM) are used to reduce control line loading, then control line loading is balanced, but the device complexity and number of buffering components increases
Solution Approach 1:
The patent extracts the buffering function from separate buffer components and integrates it directly into the memory device sets themselves. Each memory device set includes its own control buffer that interfaces with the dedicated control bus, eliminating the need for separate module-level buffer components found in RDIMM and FBDIMM designs.
3Ease of operation
If dedicated serial data and control busses with same net topology are implemented for each memory device set, then loading balance is achieved and wiring is simplified, but the number of signal lines increases compared to shared bus approaches
Solution Approach 1:
The patent combines multiple functions into the dedicated control bus for each memory device set. The control bus simultaneously handles command transmission, address routing, and control signaling, replacing what would otherwise require multiple separate signal lines in a shared bus configuration.
Data Source
AI summary
A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further includes respective dedicated serial data and control busses configured to couple respective ones of the memory device sets to a memory controller external to the at least one memory module. The dedicated serial data and control busses may be configured to provide unbuffered access to the individual memory devices from the memory controller. In other embodiments, dedicated data busses are provided to an external control buffer and dedicated control busses are provided to a control buffer in the module.