Deep Bitline Implant for Program Disturb Reduction
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Solution Overview
Problem
As semiconductor devices are scaled down, they face the challenge of 'program disturb' where adjacent memory cells are erroneously programmed due to electron migration, leading to unwanted programming of neighboring cells.
Innovation Solution
Implementing a deep bitline implant process with high energy arsenic implantation to create deeper drain junctions, which increases the distance electrons need to travel, thereby reducing program disturb and allowing for more devices to be packed in a smaller area without false programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If shallow ion implantation is used to scale down device dimensions, then manufacturing precision is improved, but program disturb increases due to electron migration
Solution Approach 1:
Instead of continuing to shallow the implant to achieve better scaling precision, the invention inverts the approach by performing a deep implantation. This counterintuitive solution creates a deeper drain junction that actually prevents electron migration to adjacent cells, thereby solving the program disturb problem while maintaining manufacturing precision through controlled deep implantation processes.
2Productivity
If device dimensions are scaled down to increase packing density, then productivity is improved, but program disturb occurs due to shorter electron migration paths
Solution Approach 1:
The invention addresses the two-dimensional scaling problem by introducing a vertical dimension solution. Instead of only reducing lateral dimensions to increase density, the patent performs deep vertical implantation to create a drain junction that extends deeper into the substrate. This vertical extension increases the electron migration path length without sacrificing lateral packing density, thereby maintaining productivity while improving reliability.
3Reliability
If deep bitline implant is performed to prevent program disturb, then reliability is improved, but device complexity increases due to additional implantation steps
Solution Approach 1:
The invention merges the deep bitline implantation with the existing shallow source/drain implantation process. By performing the deep implantation of arsenic or phosphorus at a different energy level and angle, and then combining it with the shallow implantation in a single process flow, the patent achieves program disturb prevention without significantly increasing overall device complexity. The merged process creates both the deep drain junction and the shallow source/drain regions in an integrated manner.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deep bitline implant process effectively minimizes short channel effects and prevents erroneous programming of adjacent memory cells, enabling higher packing density and improved performance in memory devices.
Implementation Method 1
A typical process of manufacturing these active areas in a metal-oxide-semiconductor-field-effect-transistor (MOSFET) requires ion implanting of the source and drain
Data Source
AI summary
A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.