Deep Color Video Processing in Single Link Clock Domain
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Solution Overview
Problem
Conventional methods for processing deep color video require the generation of a local pixel clock domain using phase locked loop circuitry, which increases manufacturing costs, power consumption, and design complexity.
Innovation Solution
The conversion and processing of deep color video are achieved in a single link clock domain without the need for phase lock loop circuitry, by converting dense video data to a sparse format where a pixel is transferred in one cycle of the link clock signal and null data is inserted to fill empty cycles, allowing for valid data signal generation to distinguish between valid and null data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional color depth conversion methods are used with phase locked loop circuitry to generate a local pixel clock, then color depth conversion can be performed, but chip area requirements increase, power consumption increases, and design complexity increases
Solution Approach 1:
The patent extracts and eliminates the phase locked loop circuitry from the system by performing color depth conversion directly in the link clock domain. This removes the unnecessary local pixel clock generation hardware, reducing chip area while maintaining conversion capability through alternative timing mechanisms
Solution Approach 2:
The link clock domain is made multi-functional by using it for both video data transmission and color depth conversion operations. This eliminates the need for a separate local pixel clock domain, reducing overall chip area requirements while maintaining full conversion functionality
2Ease of manufacture
If phase locked loop circuitry is used to generate a local pixel clock for deep color video processing, then color depth conversion is enabled, but power consumption increases
Solution Approach 1:
The phase locked loop circuitry is completely removed from the system architecture. Power consumption is reduced by performing all color depth conversion operations in the existing link clock domain without requiring additional clock generation hardware that would consume power
Solution Approach 2:
The link clock domain serves dual purposes: transmitting video data and performing color depth conversion. This eliminates the need for separate power-consuming pixel clock generation circuitry while maintaining full deep color video processing capability
3Adaptability or versatility
If phase locked loop circuitry is used to generate a local pixel clock for color depth conversion, then conversion between different color depths is possible, but device complexity increases
Solution Approach 1:
The complex phase locked loop circuitry is removed entirely. Color depth conversion is achieved through simpler data formatting operations in the link clock domain, including inserting null data and using valid data signals, which significantly reduces design and verification complexity
Solution Approach 2:
The link clock domain is utilized for multiple functions including video data transmission and color depth conversion. This eliminates the need for separate pixel clock generation infrastructure, reducing overall device complexity while maintaining conversion flexibility between different color depths
4Productivity
If dense video data format is used for deep color video, then bandwidth is efficient, but processing requires additional clock domain conversion
Solution Approach 1:
The link clock domain is made multi-functional to handle both dense video data transmission and color depth conversion operations. This allows the system to maintain bandwidth efficiency while performing processing operations directly in the existing clock domain without additional conversion complexity
Data Source
AI summary
Embodiments of the invention are generally directed to conversion and processing of deep color video in a single clock domain. An embodiment of a method includes receiving one or more video data streams, the one or more video data streams including a first video data stream, the first video data stream being clocked at a frequency of a link clock signal. The method further includes converting the first video data stream into a converted video data stream having a modified data format, wherein the modified data format includes transfer of a single pixel of data in one cycle of the link clock signal and the insertion of null data to fill empty cycles of the converted video data stream, and generation of a valid data signal to distinguish between valid video data and the null data in the converted video data stream. The method further includes processing the converted video data stream according to the frequency of the link clock signal to generate a processed data stream from the converted video data stream, wherein processing includes using the valid data signal to identify valid video data.