Deep Drain Source Cavities for Transistor Dopant Placement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in fabricating integrated circuits, particularly MOS transistors, lies in achieving reduced gate length while maintaining proper transistor performance, as high dopant concentrations are limited by solid solubility and anneal process constraints, leading to dopant diffusion and blurring of dopant profiles, which affects conductivity and capacitance, and the ion blocking capability of the gate electrode restricts dopant placement.
Innovation Solution
The technique involves recessing drain and source regions to enhance ion blocking capability by forming cavities with different lateral offsets for N-channel and P-channel transistors, using sidewall spacers to control dopant penetration depth and applying a strain-inducing semiconductor alloy, allowing for reduced implantation energies and improved dopant positioning without compromising channel region integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed to achieve high dopant concentration in shallow junction regions, then conductivity is improved, but dopant diffusion during annealing blurs the dopant profile and reduces conductivity in deeper regions
Solution Approach 1:
The drain and source regions are divided into two distinct zones: shallow junction regions with high dopant concentration for conductivity, and deeper regions with lower dopant concentration to maintain profile definition. This segmentation allows each region to optimize its function without compromising the other.
Solution Approach 2:
Different dopant concentrations are applied to different spatial locations within the drain and source regions. The shallow regions near the channel receive high dopant concentration for low resistance, while deeper regions receive lower concentration to maintain sharp junction profiles and reduce parasitic effects.
2Reliability
If high anneal temperature is used to activate dopants and recrystallize lattice damage, then dopant activation and crystal recovery are improved, but dopant diffusion increases and reduces dopant concentration at PN junction areas
Solution Approach 1:
The dopant profile is pre-established through selective ion implantation before annealing occurs. By carefully controlling the implantation depth and concentration distribution in advance, the subsequent annealing process activates dopants without significantly altering the predetermined profile shape, thus maintaining dopant concentration at critical junction areas.
3Speed
If gate length is reduced to obtain smaller and faster transistor elements, then transistor speed and packing density are improved, but ion blocking capability of the gate electrode is reduced, limiting dopant placement
Solution Approach 1:
The problem of limited dopant placement due to reduced gate length is solved by transitioning from a two-dimensional implantation approach to a three-dimensional approach using cavities. By etching cavities that extend beneath the gate electrode and performing implantation into these cavities, dopants can be placed at desired locations without being blocked by the gate, thus maintaining precision despite reduced gate length.
4Reliability
If deep drain and source regions are formed to reduce junction capacitance, then transistor performance is improved, but process complexity increases due to sophisticated implantation techniques required
Solution Approach 1:
The formation of deep drain and source regions is achieved by segmenting the process into distinct steps: cavity formation, selective implantation into cavities, and subsequent processing. This segmentation simplifies each individual step while achieving the overall goal of reducing junction capacitance through extended depletion regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by increasing dopant penetration depth and reducing junction capacitance, while maintaining efficient strain induction in P-channel transistors and minimizing performance degradation in N-channel transistors, thus optimizing transistor dimensions and conductivity.
Implementation Method 1
the ion blocking capability of the gate electrode restricts dopant placement
Implementation Method 2
applying a strain-inducing semiconductor alloy, allowing for reduced implantation energies and improved dopant positioning
Data Source
AI summary
Deep drain and source regions of an N-channel transistor may be formed through corresponding cavities, which may be formed together with cavities of a P-channel transistor, wherein the lateral offsets of the cavities may be adjusted on the basis of an appropriate reverse spacer regime. Consequently, the dopant species in the N-channel transistor extends down to a specific depth, for instance down to the buried insulating layer of an SOI device, while at the same time providing an efficient strain-inducing mechanism for the P-channel transistor with a highly efficient overall manufacturing process flow.