Deep Gate-All-Around Ge Channel Structure for Leakage Suppression
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Solution Overview
Problem
Conventional methods for fabricating tri-gate transistors on bulk silicon substrates face challenges in aligning metal gate electrodes with source and drain extension tips, leading to issues like punch-through and unwanted gate capacitance, and struggle to effectively suppress junction leakage, especially in germanium-based devices where parasitic leakage is prevalent.
Innovation Solution
The implementation of a deep gate-all-around structure, which extends the gate electrode stack below the source and drain regions, leveraging voltage threshold differences between Ge and SiGe layers to suppress leakage and reduce gate capacitance, while simplifying the fabrication process and improving interface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional tri-gate transistor fabrication is used on bulk silicon substrates, then manufacturing cost is reduced and fabrication process is simplified, but alignment between metal gate electrode and source/drain extension tips becomes difficult leading to punch-through and unwanted gate capacitance
Solution Approach 1:
The gate electrode stack extends vertically into the lower layer of the hetero-structure, utilizing the depth dimension to achieve all-around coverage of the channel region. This vertical extension enables the gate to wrap around the channel from multiple dimensions, providing superior control without requiring precise lateral alignment between gate and source/drain extensions.
Solution Approach 2:
The patent employs a hetero-structure composed of multiple layers with different compositions (Ge channel layer, SiGe lower layer, and upper layer) to create the deep gate-all-around transistor. The composite material structure enables both simplified fabrication and precise electrical control by leveraging the different properties of each material layer.
2Ease of manufacture
If conventional tri-gate structures are used, then fabrication is simpler, but junction leakage suppression is insufficient especially in germanium-based devices
Solution Approach 1:
The gate electrode stack extends vertically into the lower layer, creating a deep all-around structure that provides leakage suppression from multiple dimensions. This vertical extension into the SiGe lower layer creates effective electrical isolation and prevents parasitic leakage paths that plague conventional planar and tri-gate structures.
Solution Approach 2:
The SiGe lower layer acts as an intermediary between the Ge channel layer and the substrate, providing a transition region that helps suppress leakage. The hetero-structure design uses this intermediate layer to manage electrical properties and reduce parasitic effects while maintaining fabrication simplicity.
3Reliability
If metal gate electrode is deeper than source and drain extension tips, then gate control is improved, but unwanted gate capacitance parasitics are generated
Solution Approach 1:
The gate electrode stack is positioned to extend into the lower layer specifically in the channel region, providing localized deep control where it is most needed. This selective vertical extension achieves superior gate control over the channel while the all-around structure minimizes parasitic capacitance by eliminating exposed gate surfaces.
Solution Approach 2:
The hetero-structure with Ge channel layer and SiGe lower layer enables the gate to achieve deep control without excessive parasitic capacitance. The different material properties of the composite structure allow the gate to extend vertically for control while the material interfaces and all-around configuration reduce unwanted electrical effects.
Data Source
AI summary
Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.