Deep Inner Spacer Structure for Multi-Gate Transistor Isolation
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Solution Overview
Problem
Existing multi-gate MOSFET devices, particularly multi-bridge-channel (MBC) transistors, face challenges in forming inner spacer features that adequately separate the gate structure from the source/drain features, leading to potential electrical shorts and lattice defects due to lattice mismatch between semiconductor layers.
Innovation Solution
The formation of MBC transistors with deep inner spacer features that extend into the buffer layer, ensuring physical separation of the gate structure from the source/drain features, and incorporating a buffer layer to reduce lattice defects by using a vertical stack of germanium-tin (GeSn) or silicon germanium (SiGe) nanostructures with undoped germanium buffer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inner spacer features are formed in MBC transistors, then the gate structure is separated from source/drain features, but electrical shorts occur and lattice defects arise due to insufficient separation depth
Solution Approach 1:
The patent extends the inner spacer features vertically into the buffer layer beneath the channel layers, transitioning from conventional shallow spacers to deep spacers that penetrate through the channel layer thickness. This vertical dimensionality change provides adequate electrical isolation between gate and source/drain regions while maintaining lateral spacing requirements.
Solution Approach 2:
The deep inner spacer features are formed before the gate structure is completed, ensuring that the separation structure is already in place to prevent electrical shorts. The spacers are formed as part of the preliminary fabrication sequence, allowing subsequent gate formation to proceed without risk of electrical interference with source/drain regions.
2Area of stationary object
If the gate structure extends close to source/drain features for compact design, then device area is reduced, but electrical shorts occur due to insufficient separation
Solution Approach 1:
By extending spacers vertically into the buffer layer, the patent achieves adequate electrical isolation without requiring increased lateral spacing. This allows the gate structure to maintain compact lateral dimensions while gaining vertical separation depth, effectively decoupling area reduction from isolation requirements.
3Adaptability or versatility
If channel layers and sacrificial layers are formed with different lattice constants, then device functionality is achieved, but lattice defects occur due to lattice mismatch
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the substrate and the channel/sacrificial layer stack. This buffer layer serves as a transition medium that accommodates lattice mismatch between different material compositions, reducing dislocation propagation and defect formation while allowing diverse material combinations for device functionality.
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate, a plurality of inner spacer features interleaving the plurality of nanostructures. The plurality of nanostructures are arranged along a direction perpendicular to the substrate. The plurality of inner spacer features include a bottommost inner spacer feature and upper inner spacer features disposed above the bottommost inner spacer feature. The first height of the bottommost inner spacer feature along the direction is greater than a second height of each of the upper inner spacer features.