Deep-Junction LGAD Wafer Bonding for Fine-Pitch Detection
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Solution Overview
Problem
Conventional low-gain avalanche detectors (LGADs) face limitations in granularity due to the high-field layer breakdown between segmented implants, restricting their application beyond time-stamping in high-luminosity LHC upgrades, and other scientific pursuits requiring finer spatial resolution.
Innovation Solution
The development of deep-junction LGADs (DJ-LGADs) involves manufacturing semiconductor substrates with deep p-n junctions, achieved through techniques like wafer bonding and epitaxial layering, allowing for the burial of a planar p-n junction several microns below the surface and enabling reduced granularity scales without the need for Junction Termination Extension (JTE).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional LGAD structure with high-field layer just below cathode is used, then time-stamp resolution of +/-30 ps is achieved, but granularity is limited to 1x1 mm2 due to breakdown between implants requiring JTE
Solution Approach 1:
The patent moves the p-n junction from the surface level to a deep subsurface position (several micrometers below the surface). This dimensional change in the vertical direction allows the high-field gain region to be positioned away from the implant regions, eliminating the need for JTE and enabling finer granularity down to 50x50 μm2 while preserving the time-stamp resolution capability.
Solution Approach 2:
The patent performs preliminary doping to create deep p+ and n+ regions before forming the final device structure. By pre-positioning the high-field gain region at depth through ion implantation and thermal processing, the subsequent device fabrication can proceed with finer surface segmentation without worrying about breakdown constraints that would otherwise limit granularity.
2Reliability
If JTE is added to isolate implants in conventional LGAD, then breakdown between implants is prevented, but area of suppressed gain increases by order 100 μm limiting granularity
Solution Approach 1:
The patent extracts the high-field gain region from the surface level where it conflicts with implant isolation requirements, and relocates it to a deep subsurface position. This separation in the vertical dimension eliminates the need for JTE structures, preventing breakdown between implants without creating suppressed gain areas, thereby enabling 50x50 μm2 granularity.
3Length of stationary object
If deep junctions are formed using conventional methods, then substrate depth is increased, but manufacturing complexity increases and existing processes cannot achieve required depth
Solution Approach 1:
The patent changes the energy parameter of ion implantation to achieve deep doping profiles. By using higher ion implantation energies (e.g., >1 MeV), the dopant ions penetrate much deeper into the substrate, creating p+ and n+ regions at several micrometers depth. This parameter change enables deep junction formation using modified versions of existing semiconductor manufacturing processes, avoiding the need for entirely new fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the granularity of LGADs to 50×50 μm², maintaining superior temporal resolution and frame rate while avoiding crosstalk and recovery-time limitations, enabling broader scientific applications such as 4D tracking and next-generation X-ray imaging.
Implementation Method 1
forming at least one p+ region (n+ region) on a front side of a p-type (n-type) high-resistance wafer; and forming at least one n+ region (p+ region) on a front side of a n-type (p-type) high-resistance wafer
Implementation Method 2
bonding the front sides of the high-resistance wafers to form a wafer assembly having at least one deep p-n junction at a depth of at least 1 micron from the backside of the n-type (p-type) high-resistance wafer
Implementation Method 3
applying a p-type (n-type) layer having a thickness in the range of 1-10 microns on the front side of the p-type (n-type) structure, to thereby form a semiconductor substrate having at least one deep p-n junction
Data Source
AI summary
A method of manufacturing a semiconductor substrate having a deep junction, forming at least one p+ region (n+ region) on a front side of a p-type (n-type) high-resistance wafer: and forming at least one n+ region (p+ region) on a front side of a n-type (p-type) high-resistance wafer. The method further includes aligning the at least one p+ region (n+ region) on a front side of a p-type (n-type) high-resistance wafer with the at least one n+ region (p+ region) on a front side of a n-type (p-type) high-resistance wafer: and bonding the front sides of the high-resistance wafers to form a wafer assembly having at least one deep p-n junction at a depth of at least 1 micron from the backside of the n-type (p-type) high-resistance wafer.