Deep-Layer Doping Profile for Breakdown Voltage in Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor devices face challenges in suppressing the decrease in breakdown voltage while preventing breakage of the gate insulating film and minimizing the increase in size along the stacking direction of the drift layer and base layer.
Innovation Solution
The semiconductor device incorporates a first deep layer with a specific impurity concentration profile, featuring a high-concentration region and a low-concentration region, where the high-concentration region has a peak that is not depleted in the off state, and the low-concentration region has a gradual impurity concentration change, with a shorter first length compared to a second length, to enhance breakdown voltage and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a deep layer is disposed below the trench gate structure in the drift layer, then breakdown voltage is enhanced, but the device size increases in the stacking direction
Solution Approach 1:
The patent applies local quality by creating a deep layer with non-uniform impurity concentration distribution. The high-concentration region is localized at specific depths to provide breakdown voltage enhancement, while the low-concentration region minimizes the overall depth occupation. This localized optimization allows the deep layer to enhance breakdown voltage without proportionally increasing device size in the stacking direction.
Solution Approach 2:
The patent utilizes parameter changes by varying the impurity concentration profile within the deep layer. By controlling the impurity concentration to have a high-concentration region and a low-concentration region with specific gradient characteristics, the deep layer achieves effective breakdown voltage enhancement while limiting the extension depth, thus reducing the increase in device size along the stacking direction.
2Strength
If the impurity concentration gradient in the deep layer is steep, then breakdown voltage is improved, but the gate insulating film may break due to high electric field stress
Solution Approach 1:
The patent applies local quality by spatially differentiating the impurity concentration within the deep layer. The high-concentration region provides the necessary breakdown voltage enhancement, while the low-concentration region with controlled gradient is positioned to mitigate electric field stress on the gate insulating film. This spatial differentiation allows simultaneous achievement of high breakdown voltage and gate insulating film reliability.
Solution Approach 2:
The patent utilizes parameter changes by optimizing the impurity concentration profile parameters. The gradient of impurity concentration change is controlled to be within a specific range in the low-concentration region, which reduces electric field stress on the gate insulating film while maintaining adequate breakdown voltage through the high-concentration region. This parameter optimization resolves the contradiction between breakdown voltage enhancement and gate insulating film protection.
Data Source
AI summary
In a semiconductor device, a first deep layer has a high-concentration region and a low-concentration region in a concentration profile of an impurity concentration along a depth direction. The high-concentration region has a high concentration peak at which an impurity concentration is maximum, and includes a region that is not depleted in an off state. The low-concentration region is closer to a high-concentration layer than the high-concentration region, has a region in which a gradient of change in impurity concentration is smaller than a predetermined value, and is depleted in the off state. A first length between a first position closest to a base layer in the first deep layer and a second position of the high concentration peak is shorter than a second length between the second position and a third position closest to the base layer in the low-concentration region.