Deep-Layer FET Structure for High Breakdown and Low On-Resistance
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Solution Overview
Problem
Field effect transistors face challenges in achieving a balance between high breakdown voltage and low on-resistance due to electric field concentration and electron flow path limitations in existing designs.
Innovation Solution
The design incorporates p-type and n-type deep layers with specific dimensions and orientations, where p-type deep layers protrude downward from the body layer and n-type deep layers are disposed in spacing portions, with n-type deep layers having a higher impurity concentration than the drift layer, to manage electric field concentration and electron flow resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If p-type deep layers are used to control electric field concentration, then breakdown voltage is improved, but on-resistance increases due to limited electron flow paths
Solution Approach 1:
The invention divides the deep layer structure into alternating p-type and n-type deep layers. The p-type deep layers (36) control electric field concentration for high breakdown voltage, while the n-type deep layers (37) positioned in spacing portions provide additional electron flow paths to maintain low on-resistance. This segmentation allows independent optimization of both contradictory requirements.
Solution Approach 2:
The invention applies different impurity concentrations and types locally: p-type deep layers have high p-type impurity concentration for electric field control, while n-type deep layers have high n-type impurity concentration for electron conduction. The drift layer has lower n-type impurity concentration. This local quality differentiation enables simultaneous achievement of high breakdown voltage and low on-resistance.
2Reliability
If n-type deep layers with high impurity concentration are added to reduce on-resistance, then electron flow is improved, but breakdown voltage may be compromised due to electric field concentration
Solution Approach 1:
The alternating structure of p-type and n-type deep layers allows the n-type layers to provide electron flow paths without creating continuous high-impurity regions that would compromise breakdown voltage. The p-type layers act as barriers that prevent excessive electric field concentration despite the presence of high-concentration n-type layers.
Solution Approach 2:
The p-type deep layers serve as intermediary structures between the n-type deep layers and the drift layer. They mediate the electric field distribution, preventing the high-concentration n-type deep layers from causing excessive electric field concentration that would reduce breakdown voltage, while still allowing electron flow through the n-type layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a high breakdown voltage while maintaining low on-resistance by controlling depletion layers and electron flow paths, enhancing the overall performance of the field effect transistor.
Implementation Method 1
A drift layer having a lower n-type impurity concentration than each of the n-type deep layers is in contact with lower surfaces of the n-type deep layers
Data Source
AI summary
A field effect transistor includes a plurality of p-type deep layers and a plurality of n-type deep layers. Each of the p-type deep layers protrudes downward from a body layer, extends along a first direction that intersects the trench when a semiconductor substrate is viewed from above, and is disposed to have a spacing portion therebetween in a second direction that is orthogonal to the first direction when the semiconductor substrate is viewed from above. Each of the n-type deep layers is disposed in the spacing portion. A drift layer has a lower n-type impurity concentration than each of the n-type deep layers. A dimension of each of the n-type deep layers in a thickness direction of the semiconductor substrate is larger than a dimension of each of the n-type deep layers in the second direction.