Information Processing Circuit for Deep Learning Adaptability
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Solution Overview
Problem
Dedicated hardware for deep learning neural networks has a fixed circuit configuration, making it difficult to adapt to increased training data or more advanced network configurations without modifying the hardware.
Innovation Solution
An information processing circuit comprising a first fixed circuit for deep learning operations and a second programmable accelerator, integrated with a calculation result integration circuit, allowing for adjustable input/output characteristics without altering the hardware configuration, using parameter value output circuits and sum-of-product operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed circuit configuration is used for deep learning hardware, then processing speed and power consumption are optimized, but adaptability to different network configurations and increased training data is lost
Solution Approach 1:
The deep learning processing is segmented into two distinct paths: a fixed circuit path for standard operations and a programmable accelerator path for adaptive operations. This segmentation allows each path to be optimized for its specific function while maintaining overall system flexibility.
Solution Approach 2:
The system introduces dynamic configurability through the programmable accelerator, which can be reconfigured via software to handle different network architectures and training requirements, contrasting with the static fixed circuit path.
2Use of energy by moving object
If a fixed circuit configuration is used for deep learning hardware, then power consumption is reduced, but the ability to handle increased training data and advanced DNNs is limited
Solution Approach 1:
The processing workload is segmented between the energy-efficient fixed circuit for routine operations and the programmable accelerator for complex, data-intensive tasks requiring adaptability.
Solution Approach 2:
The programmable accelerator serves multiple functions by being reconfigurable to handle different network configurations and training scenarios, making the system universal while the fixed circuit handles specific efficient operations.
3Productivity
If dedicated hardware with fixed circuit configuration is used, then processing efficiency is improved, but flexibility to change input/output characteristics without hardware modification is lost
Solution Approach 1:
The system combines static fixed circuits with dynamically reconfigurable programmable accelerators, allowing input/output characteristics to be changed through software configuration rather than hardware modification.
Solution Approach 2:
Instead of physically modifying hardware circuits, the system uses software-based configuration copies that can be loaded onto the programmable accelerator to change operational characteristics without altering the physical hardware.
Data Source
AI summary
The information processing circuit 80 includes a first information processing circuit 81 that performs layer operations in deep learning, a second information processing circuit 82 that performs the layer operations in deep learning on input data by means of a programmable accelerator, and an integration circuit 83 integrates a calculation result of the first information processing circuit 81 with a calculation result of the second information processing circuit 82, and output an integration result, wherein the first information processing circuit 81 includes a parameter value output circuit 811 in which parameters of deep learning are circuited, and a sum-of-product circuit 812 that performs a sum-of-product operation using the input data and the parameters.