Deep N-Well Cell Placement for Dense Analog-Digital Layouts

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Solution Overview

Problem

As technology advances and the demand for scaled integrated circuits (ICs) increases, IC manufacturers face challenges in fitting a growing number of analog and digital cells into smaller IC layout designs, particularly in optimizing the spacing and protecting digital cells from noise generated by adjacent analog cells.

Innovation Solution

The placement of analog and digital cells in a common well region, such as a deep n-well region, optimizes the spacing between them, improving it from 3 μm to 1 μm and provides a guard ring to shield digital cells from noise, using a deep n-well region doped with n-type dopants and electrically coupled to a reference voltage supply through multiple metallization layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If analog and digital cells are placed in separate regions with larger spacing, then noise interference is reduced, but integration density decreases

Engineering Contradiction:
Improvenoise interferenceVSAvoidintegration density
Core Design Contradiction:
Object-affected harmful factorsVSQuantity of substance

Solution Approach 1:

A deep n-well region is introduced as an intermediary structure between analog and digital cells. This well region acts as a mediator that provides noise shielding to digital cells while enabling closer placement, thus resolving the contradiction between noise reduction and integration density improvement

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If analog and digital cells are placed closer together, then integration density improves, but noise interference increases

Engineering Contradiction:
Improveintegration densityVSAvoidnoise interference
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The deep n-well region serves as a protective intermediary that enables close placement of analog and digital cells while maintaining noise isolation. By introducing this intermediate structure, the patent achieves high integration density without sacrificing noise protection

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-affected harmful factors

If digital cells are surrounded by a guard ring structure, then noise shielding is improved, but device complexity increases

Engineering Contradiction:
Improvenoise shieldingVSAvoiddevice complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The guard ring function is merged with the deep n-well region structure. Instead of adding a separate guard ring structure, the deep n-well itself provides the shielding function, combining the well region and guard ring into a single integrated structure that reduces complexity while maintaining noise shielding effectiveness

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the integration density of analog and digital cells while maintaining signal integrity by reducing noise interference, allowing closer proximity of cells and improving manufacturing efficiency.

Implementation Method 1

The placement of analog and digital cells in a common well region, such as a deep n-well region, optimizes the spacing between them, improving it from 3 μm to 1 μm and provides a guard ring to shield digital cells from noise

Methodology Applied
Scientific EffectElectrical shielding: Faraday Cage

Data Source

PatentUS20240371942A1Cell placement optimization
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240371942A1 patent drawing
  • US20240371942A1 patent drawing
  • US20240371942A1 patent drawing

AI summary

The present disclosure describes structure with a substrate, a first well region, a second well region, and a third well region. The first well region is in the substrate. The second well region is in the first well region and includes a first source/drain (S/D) region. The third well region is in the substrate and adjacent to the first well region. The third well region includes a second S/D region, where a spacing between the first and second S/D regions is less than about 3 μm.