Deep Nwell Implantation Through Gate Stack
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Solution Overview
Problem
The existing semiconductor fabrication processes for CMOS integrated circuits require a separate mask pattern for deep Nwells, increasing cost and cycle time, especially in SRAMs where NMOS driver/pass-gate transistors need screening for Positive Bias Temperature Instability (PBTI) without an added masking level.
Innovation Solution
The method involves implanting deep Nwells through the gate stack for NMOS devices, optionally for PMOS devices, without the need for additional masks, allowing for shallower DNwell depth below the NMOS gate stack, enabling back bias capability for PBTI screening in SRAMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a separate mask pattern is used for deep Nwell implantation, then the DNwell can be formed with proper depth control, but the fabrication cost and cycle time increase
Solution Approach 1:
The patent combines the DNwell implantation process with the existing gate dielectric formation process by using the gate dielectric layer itself as the masking layer. This eliminates the need for a separate DNwell mask pattern, reducing fabrication complexity while maintaining proper DNwell depth control through the gate dielectric thickness
Solution Approach 2:
The gate dielectric layer serves multiple functions: it acts as both the gate insulator and the masking layer for DNwell implantation. This multi-functionality eliminates the need for dedicated masking materials and processes, streamlining the fabrication workflow
2Manufacturing precision
If a separate mask pattern is used for deep Nwell implantation, then the DNwell can be formed with proper depth control, but the fabrication cycle time increases
Solution Approach 1:
The patent merges the DNwell implantation step with the gate dielectric formation sequence, allowing both processes to be completed within the same fabrication cycle without adding extra masking and unmasking steps
Solution Approach 2:
The gate dielectric layer is formed first to establish the masking structure before DNwell implantation occurs. This preliminary action ensures that the masking layer is already in place and properly configured, eliminating the need for separate masking preparation steps
3Device complexity
If DNwell is implanted through the gate stack, then the masking complexity is reduced, but the DNwell depth below the gate stack becomes shallower
Solution Approach 1:
The patent adjusts the implantation energy and angle parameters to compensate for the gate electrode blocking effect. By optimizing these parameters, the DNwell achieves the required effective depth for back-bias functionality despite the shallower physical depth below the gate stack
Solution Approach 2:
The DNwell depth is optimized locally under different regions: shallower under the gate stack (where the gate electrode blocks implantation) and deeper under the source/drain regions (where full implantation depth is achieved). This local variation in depth is sufficient to provide the required back-bias capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the need for a dedicated DNwell masking level, reducing fabrication costs and cycle time while providing effective PBTI screening for NMOS transistors, enhancing the reliability of CMOS integrated circuits.
Implementation Method 1
a retrograde implant of an n-type species includes implanting through the gate stack for NMOS devices to form a DNwell
Data Source
AI summary
A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.