Deep N-well Non-volatile Memory Cell for Logic Integration
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Solution Overview
Problem
Existing non-volatile memory cells integrated with logic components face challenges such as high manufacturing costs, compromised data retention, and added complexity due to incompatibility with common logic processes, requiring special circuits and higher voltage transistors.
Innovation Solution
An electrically programmable and erasable non-volatile memory cell with a deep N-well is developed, using transistors with two gate-oxide thicknesses to isolate the memory cell from the substrate, allowing fabrication with common silicon foundry processes, and employing hot channel electron tunneling for programming and Fowler-Nordheim tunneling for erasing, without the need for additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory cells are integrated with logic components using specialized processes, then memory functionality is achieved, but manufacturing cost increases and process compatibility is lost
Solution Approach 1:
The patent changes the electrical parameters of the substrate by introducing a deep N-well structure that raises the substrate potential to match the logic circuit supply voltage (e.g., 3.3V). This parameter change allows the memory cell to operate with standard logic process transistors without requiring specialized high-voltage processing, thereby maintaining process compatibility while achieving reliable data retention through proper voltage isolation.
Solution Approach 2:
The deep N-well acts as an intermediary structure between the memory cell and the logic circuit substrate. It provides electrical isolation and potential matching, enabling the memory cell to function with standard logic process components without direct electrical conflict, thus resolving the contradiction between specialized memory requirements and standard logic process compatibility.
2Reliability
If additional processing steps are added to logic manufacturing processes for memory integration, then memory cell functionality is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The deep N-well structure serves multiple functions simultaneously: it provides electrical isolation for the memory cell, raises the substrate potential to match logic circuit voltages, and enables compatibility with standard logic process transistors. By consolidating these functions into a single structural element formed during standard logic fabrication, the patent avoids adding separate processing steps while achieving reliable memory functionality.
3Ease of operation
If high voltage is applied to PMOS transistor for programming, then programming capability is achieved, but data retention is compromised without thick oxide transistors
Solution Approach 1:
The patent applies local quality by creating a localized high-potential region through the deep N-well structure. The substrate potential under the memory cell is raised to match the logic supply voltage, while other regions of the chip maintain their original voltage levels. This localized potential adjustment enables the memory cell to tolerate programming voltages using standard-thickness oxide transistors, achieving both programming capability and data retention without requiring thick oxide devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of memory cells with improved data retention lasting approximately 10 years or longer, reduced manufacturing complexity, and compatibility with deep sub-micron technologies, while maintaining compatibility with logic processes, thus reducing costs and enhancing integration with logic components.
Implementation Method 1
a deep N-well to isolate the memory cell from the substrate
Implementation Method 2
employing hot channel electron tunneling for programming
Implementation Method 3
Fowler-Nordheim tunneling for erasing
Data Source
AI summary
An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.