Common Deep N-Well Biasing for Compact Multi-Voltage Cells
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Solution Overview
Problem
Existing semiconductor devices with multiple power domains require large gaps between non-deep wells configured for different power domains, leading to wasted space and increased footprint.
Innovation Solution
Incorporating a deep N-well biased to the greater of the two power domain voltages, allowing for a significantly smaller gap between non-deep wells, thereby reducing the overall area/footprint of the cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate non-deep wells are used for different power domains with separate biasing, then voltage translation between power domains is achieved, but area/footprint increases due to large gaps between wells
Solution Approach 1:
The patent merges multiple non-deep wells configured for different power domains into a single common deep n-well structure. By combining the wells and using a maximum voltage selector circuit to bias the deep well to the greater of VDD1 or VDD2, the design eliminates the need for large gaps between separate wells, thereby reducing the overall cell region area while maintaining proper voltage translation functionality.
Solution Approach 2:
The patent changes the biasing parameter of the deep n-well from separate domain-specific voltages to a unified maximum voltage (max(VDD1, VDD2)). This parameter change allows the deep well to properly bias PMOS transistors across different power domains without requiring large isolation gaps, thus reducing area while maintaining voltage translation capability.
2Reliability
If large gaps are placed between non-deep wells for separate biasing, then proper voltage domain isolation is achieved, but device complexity increases
Solution Approach 1:
The patent merges multiple separate well structures into a single common deep n-well, thereby simplifying the overall device structure. The maximum voltage selector circuit provides unified biasing that maintains proper voltage domain isolation without requiring complex separate well configurations and large gaps between them.
Solution Approach 2:
The common deep n-well serves multiple functions: it biases PMOS transistors for both power domains, provides voltage domain isolation through the maximum voltage selector circuit, and reduces structural complexity. This multi-functional approach eliminates the need for separate dedicated wells for each power domain.
3Reliability
If non-deep wells are separated for different power domains, then voltage level translation is maintained, but the gap between wells increases area/footprint
Solution Approach 1:
The patent combines multiple non-deep wells into a single common deep n-well structure, eliminating the gaps that would exist between separate wells. The maximum voltage selector circuit ensures that the deep well is biased to the appropriate voltage level, maintaining voltage level translation functionality while minimizing the gap area to essentially zero since the wells are merged.
Solution Approach 2:
The patent implements a nested well structure where first and second non-deep wells are formed within the common deep n-well. This nesting arrangement allows the deep well to provide a shared biasing structure for multiple power domains without requiring lateral gaps between separate wells, thereby reducing the overall area occupied by the well structures.
Data Source
AI summary
A semiconductor device includes a first conductivity-type substrate, and a cell region including: a second conductivity type deep well; first and second non-deep wells having the second conductivity-type, the first and second non-deep wells being in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first, second, third and fourth transistor-regions. The first and second transistor-regions are correspondingly in the first and second non-deep wells and include first conductivity-type first transistors. The third and fourth transistor-regions are in the third and fourth portions of the substrate which are in the deep well, and include second transistors having the second conductivity-type. The first transistor-region is configured for a first power domain. The second, third and fourth transistor-regions are configured for a second power domain that is different than the first power domain.