Deep N-well Tile Pattern Generation for CMOS Body-Bias Alignment
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Solution Overview
Problem
Existing CMOS circuit designs face challenges in efficiently managing body-bias voltage connections due to size disparities between surface and buried well features, leading to alignment and coverage issues that prior art methods fail to address effectively.
Innovation Solution
A method for generating and checking deep N-well mask patterns using a hierarchical structure of tiles, allowing for efficient data storage and computational resources, with a process flow that includes specifying tile geometry, assembling tile arrays, editing, merging, and flattening to ensure accurate and robust body-bias voltage connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional aperture formation methods are used for buried wells, then alignment with surface features can be attempted, but the size disparity between surface and buried features causes disconnected bits and width/spacing violations
Solution Approach 1:
The patent segments the aperture formation process into multiple steps: first forming a preliminary pattern at surface level, then using it as a template to form buried well apertures at depth. This segmentation allows each step to be optimized independently, ensuring both alignment accuracy and feature connectivity despite the order-of-magnitude size difference between surface and buried features.
Solution Approach 2:
The patent performs preliminary action by first forming the surface aperture pattern before forming the buried well apertures. The surface pattern serves as a pre-established template that guides the subsequent buried well formation, ensuring proper alignment and connectivity are achieved before the actual buried well fabrication begins.
2Ease of manufacture
If standard mesh generation and rules checking are used, then conventional design flows are maintained, but the method fails to accommodate the order of magnitude size disparity between surface and buried features
Solution Approach 1:
The patent introduces dynamic adaptability into the design flow by implementing size-aware mesh generation and rules checking that can adjust to the order-of-magnitude differences between surface and buried features. The system dynamically scales and adapts design rules based on the specific geometric characteristics of each feature type, maintaining ease of manufacture while achieving geometric versatility.
Solution Approach 2:
The patent changes key parameters in the mesh generation and rules checking processes to accommodate size disparities. This includes adjusting mesh densities, aperture size thresholds, and spacing rules based on whether features are at surface level or buried depth, allowing the conventional design flow to handle both small surface features and large buried features effectively.
3Loss of energy
If low operating voltages are used, then power consumption is reduced, but threshold voltage variations increase leading to increased leakage currents
Solution Approach 1:
The patent applies local quality by implementing body-biasing that can independently adjust the threshold voltage of specific transistor regions. By connecting different buried well regions to different bias potentials, the circuit can locally compensate for threshold voltage variations in individual transistors or regions, maintaining reliable operation even at low operating voltages where such variations would normally cause excessive leakage.
Data Source
AI summary
A method for the design and layout for a patterned deep N-well. A Tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.