Deep Power Rail Layout for Cell Height Reduction
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Solution Overview
Problem
The challenge in semiconductor technology is to reduce the dimensions of transistors and spacing between them to fit more transistors on a chip while maintaining low rail resistance and minimizing IR drops.
Innovation Solution
The solution involves reducing the width of power rails while increasing their height in the z-direction through separate lithographic and etching processes, allowing for cell height reduction without significantly increasing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the width of power rails is reduced to fit more transistors on chip, then the area for transistor placement increases, but the rail resistance increases and IR drops worsen
Solution Approach 1:
The patent applies dimensionality change by extending power rails into the vertical dimension (z-direction) to create taller rails. This allows the rails to maintain lower resistance while reducing their horizontal width, thereby enabling more transistors to be placed on the chip without compromising power delivery reliability.
Solution Approach 2:
The patent changes the geometric parameters of power rails by increasing their height in the z-direction while reducing their width in the horizontal plane. This parameter transformation maintains the electrical performance (low resistance) while optimizing the layout density for more transistor placement.
2Length of stationary object
If separate lithographic and etching processes are used to increase rail height, then cell height can be reduced by 5-10%, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the power rail formation into separate lithographic and etching processes. By dividing the manufacturing steps, the process can precisely control the rail height and width independently, enabling cell height reduction while managing manufacturing complexity through structured process separation.
3Quantity of substance
If transistor dimensions are scaled down to fit more transistors on chip, then the transistor count increases, but maintaining low rail resistance becomes more difficult
Solution Approach 1:
As transistor count increases through scaling, the patent compensates for the increased difficulty of maintaining low rail resistance by extending rails into the vertical dimension. This dimensional change provides additional cross-sectional area for current flow, offsetting the challenges posed by higher transistor density and enabling continued scaling.
Data Source
AI summary
A chip includes a first epitaxial (epi) layer, a first contact disposed on the first epi layer, and a rail coupled to the first contact, wherein the rail has a first height in a first direction. The chip also includes a second epi layer, a second contact disposed on the second epi layer, and a signal line, wherein the signal line has a second height in the first direction, and the first height is greater than the second height. The chip also includes a via disposed between the second contact and the signal line in the first direction.