Deep RL Verification Tuning for Rare Coverage and Bug Detection
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Solution Overview
Problem
Design verification of integrated circuits faces challenges in achieving comprehensive functional coverage, particularly for rare and complex corner cases, which are difficult and time-consuming to hit, leading to potential undetected bugs and delayed completion.
Innovation Solution
Employing deep reinforcement learning (RL) algorithms to generate targeted stimuli that adjust verification parameters, responses, and configuration settings to increase the likelihood of hitting functional coverage statements and uncover bugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional design verification techniques are used to simulate circuit designs, then the verification process can be conducted, but functional coverage is insufficient particularly for rare corner cases and the process is delayed due to IC design complexity
Solution Approach 1:
The patent implements feedback mechanisms where simulation results and coverage metrics are continuously fed back to adjust simulation parameters. The system monitors functional coverage achievement and dynamically modifies simulation configurations to target uncovered corner cases, thereby improving reliability while managing verification time through iterative optimization.
Solution Approach 2:
The patent applies parameter changes by systematically varying simulation parameters such as input signal characteristics, test stimulus patterns, and verification environment configurations. This enables the verification process to explore rare corner cases that would otherwise be missed, improving functional coverage without requiring exhaustive testing of all possible scenarios.
2Reliability
If comprehensive functional coverage is pursued to detect all bugs, then bug detection capability improves, but verification time and resource consumption increase significantly
Solution Approach 1:
The verification system performs self-service by automatically analyzing coverage gaps and autonomously adjusting simulation parameters to target uncovered functional areas. This self-directed optimization enables comprehensive bug detection without requiring manual intervention for each coverage gap, maintaining high reliability while improving verification efficiency through automated resource management.
Solution Approach 2:
The patent applies partial action by focusing verification efforts on the most critical and previously uncovered functional areas rather than attempting exhaustive testing of all possible scenarios. This selective approach achieves sufficient bug detection capability while avoiding the exponential resource consumption that would result from complete exhaustive testing.
3Reliability
If simulation parameters are manually adjusted to improve code coverage, then functional coverage may improve, but the complexity of managing multiple simulation configurations increases
Solution Approach 1:
The patent replaces manual mechanical adjustment of simulation parameters with an automated computational system. The verification environment automatically generates and manages simulation configurations based on coverage analysis, eliminating the need for manual parameter tuning and reducing the complexity of managing multiple simulation configurations while maintaining high code coverage.
Data Source
AI summary
Methods, systems, and devices for tuning a set of simulation parameters associated with a design verification environment are described that include: simulating a circuit design according to a set of simulation parameters; providing, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation parameters; receiving an output in response to the machine learning network processing the functional coverage results; and simulating the circuit design based on a recommended set of simulation parameters, wherein simulating the circuit design based on the recommended set of simulation parameters includes generating a set of component signals associated with satisfying a target functional coverage statement. In some aspects, the output includes: the target functional coverage statement associated with the circuit design; and the recommended set of the simulation parameters.


