Deep and Shallow Interconnect Lines for Lower RC Delay
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Solution Overview
Problem
The miniaturization of integrated circuits has led to stricter design and manufacturing specifications, along with challenges in reliability and performance, particularly in signal propagation delays due to resistance capacitance (RC) constants in conducting paths.
Innovation Solution
Incorporating deep lines and shallow lines in multiple conductive layers of integrated circuits, with specific depth adjustments to reduce the RC constant and optimize signal propagation by forming low resistivity and low capacitivity portions with mutation points between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If deep lines are used in conductive layers, then resistivity is reduced and signal propagation speed is improved, but capacitivity increases which can cause signal delays
Solution Approach 1:
The patent applies local quality by creating segments of deep lines and shallow lines within the same conductive path. Deep line segments are positioned where low resistivity is needed to boost signal speed, while shallow line segments are positioned where low capacitivity is needed to minimize signal delays. This localized differentiation allows each segment to optimize for its specific electrical characteristic requirement.
Solution Approach 2:
The conductive path is segmented into multiple sections with varying line depths. Rather than using a uniform depth throughout the entire path, the patent divides the path into segments that can be independently optimized. This segmentation enables the circuit to balance the trade-off between resistivity and capacitivity by assigning different depth characteristics to different segments based on their functional requirements.
2Volume of moving object
If miniaturization is pursued to reduce device size, then power consumption decreases and functionality increases, but design and manufacturing specifications become stricter and reliability challenges increase
Solution Approach 1:
The patent addresses miniaturization challenges by utilizing the vertical dimension (depth) in addition to the planar dimensions. By varying the depth of conductive lines within existing conductive layers, the patent achieves additional degrees of freedom for optimization without requiring additional horizontal space. This dimensional approach allows for performance optimization while maintaining compact device footprints.
Data Source
AI summary
An integrated circuit includes a first layer deep line and a first layer shallow line in a first conductive layer, a second layer deep line and a second layer shallow line in a second conductive layer, a first active device having an output conductively connected to the first layer deep line, and a second active device having an input conductively connected to the first layer shallow line. The first layer deep line is conductively connected to the second layer deep line without passing through a shallow line in the first conductive layer or in the second conductive layer. The first layer shallow line which is conductively connected to the second layer shallow line without passing through a deep line in the first conductive layer or in the second conductive layer. The second layer deep line is conductively connected to the second layer shallow line.