Deep Source Contact Fabrication in Planar Power MOSFETs
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Solution Overview
Problem
The challenge in fabricating planar gate power semiconductor devices lies in achieving low specific ON-resistance (RSP) and minimizing parasitic resistance, particularly in forming deep source contacts with high aspect ratios, which is complicated by metal fill and etch processes that can result in residue and seam formation, affecting the performance and reliability of power MOSFETs.
Innovation Solution
The solution involves modifying the NEXFET planar gate power FET design by replacing aluminum source contacts with silicon contacts and using a metal-filled deep source contact within an epitaxial layer, self-aligning the deep source contact trenches, and employing a double metal filler deposition/etch back method to ensure precise filling and etching, thereby reducing parasitic resistance and improving the aspect ratio of the source contact trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single metal filler deposition/etch back process is used to form deep source contacts with high aspect ratio trenches, then the manufacturing process is simpler, but metal residue and seam formation occur causing leakage and increased parasitic resistance
Solution Approach 1:
The single metal filler deposition/etch back process is segmented into multiple sequential steps: first forming an initial metal filler layer, then performing selective etching to remove metal from specific regions (sidewalls and drain area), followed by additional metal deposition to complete the fill. This multi-step segmentation enables precise control over metal placement, eliminating residue and seam formation while maintaining manufacturing feasibility.
2Reliability
If the aspect ratio of source contact trenches is increased to reduce parasitic resistance, then electrical performance improves, but metal fill and etch processing becomes significantly more difficult
Solution Approach 1:
Before attempting to fill high aspect ratio trenches with metal, the process performs preliminary selective etching to remove metal from sidewall and drain region areas first. This preliminary action creates a controlled geometry that facilitates subsequent complete metal fill without voids or seams, making the high aspect ratio trench filling manufacturable while maintaining the electrical performance benefits.
3Ease of manufacture
If metal residue remains after fill and etch back processing, then the manufacturing process is more tolerant, but leakage and shorting occur between source and drain contacts
Solution Approach 1:
The process incorporates feedback control through multiple deposition and etching cycles with intermediate inspection and adjustment. The selective etching steps are designed to remove metal residue that would cause leakage, while the subsequent complete fill ensures proper contact formation. This feedback-based iterative process achieves both manufacturing tolerance and device reliability by detecting and correcting residue issues before final device completion.
Data Source
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AI summary
A planar gate power MOSFET (100) includes a substrate (105) having a semiconductor surface (108) doped a first conductivity type, a plurality of transistor cells (cells) including a first cell (110a) and at least a second cell (110b) each having a gate stack (111a/112, 111b/112) over a body region (113). A trench has an aspect ratio of ＞ 3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) (120) from a source (127) doped a second conductivity type to the substrate. A field plate (FP) (128) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler (122) within. A drain (132) doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.