Deep Source Drain Transistor Back-Side Contact Metallization
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Solution Overview
Problem
As integrated circuits (ICs) continue to shrink, achieving low contact resistance for back-side interconnect metallization becomes challenging due to the complexity of accessing and connecting transistor structures from the back side, leading to potential performance issues.
Innovation Solution
The development of a transistor structure with deep source and drain semiconductor regions, where the back-side contact metallization passes through a lightly doped layer to reach a heavily doped layer, ensuring lower contact resistance and improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If back-side contact metallization is used to access transistor structures, then 3D chip scaling and device density are improved, but contact resistance increases
Solution Approach 1:
The patent transitions from conventional front-side contact to back-side contact metallization, utilizing the z-dimension (vertical dimension) to access transistor source/drain regions. This dimensional change enables 3D chip scaling by routing interconnects through the substrate thickness, thereby increasing device density while maintaining electrical connectivity through carefully engineered deep contact structures that penetrate the substrate to reach the active regions.
Solution Approach 2:
The patent modifies the doping concentration parameter by creating a heavily doped region at the back-side contact interface. This parameter change (increasing dopant concentration) reduces the contact resistance between the metallization and semiconductor, ensuring reliable electrical contact despite the increased contact depth required for back-side access.
2Reliability
If deep source and drain structures are formed to enable back-side contact, then contact resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary doping actions by forming a heavily doped region in the source/drain structures before final metallization deposition. This preliminary action ensures that when back-side contacts are subsequently formed, they encounter a pre-prepared low-resistance contact region, thereby reducing contact resistance without requiring complex real-time adjustments during the contact formation process.
Solution Approach 2:
The patent applies local quality by creating a heavily doped region specifically at the back-side contact interface, while maintaining different doping levels in other regions of the source/drain structures. This localized modification of doping concentration ensures low contact resistance at the critical contact point without unnecessarily complicating the overall device structure or requiring uniform changes throughout the entire transistor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient electrical contact with the transistor structure, reducing contact resistance and enhancing overall IC performance by ensuring reliable back-side metallization.
Implementation Method 1
the back-side contact metallization passes through a lightly doped layer to reach a heavily doped layer, ensuring lower contact resistance and improved connectivity
Data Source
AI summary
Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.