Deep Trench Capacitor Backside Integration via Through-Silicon-Via
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Solution Overview
Problem
Conventional deep trench capacitors consume significant silicon area and have low capacitance density, making them inefficient for on-chip decoupling, especially in back-end-of-the-line (BEOL) applications where space is limited and thinner dielectrics are beneficial.
Innovation Solution
A method for forming deep trench capacitors involves creating a through-silicon-via and a deep trench on the back side of a wafer, with a buried plate and node dielectric layer, and filling with conductive material, allowing the capacitors to be formed without occupying front-side area and enabling high capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deep trench capacitors are used, then capacitance is provided for power supply decoupling, but significant silicon area is consumed
Solution Approach 1:
The capacitor structure transitions from a planar configuration to a vertical three-dimensional structure by forming deep trenches extending into the substrate. This dimensional change allows capacitance to be generated in the vertical direction rather than consuming horizontal silicon area, resolving the contradiction between providing decoupling capacitance and minimizing area usage.
Solution Approach 2:
The capacitor structure embeds multiple functional layers within a vertical trench: conductive plates at different depths, dielectric layers between them, and connections to through-silicon vias. This nested arrangement packs multiple capacitor elements into a single vertical column, maximizing capacitance density while minimizing footprint.
2Adaptability or versatility
If BEOL capacitors are used, then wiring channel requirements are reduced, but capacitance density is low
Solution Approach 1:
The invention changes the critical parameter from lateral dimensions to vertical depth by forming trenches that extend deep into the substrate. This parameter transformation allows the capacitor to achieve high capacitance density through increased plate area in the vertical direction, compensating for the thicker dielectric inherent in BEOL processes and maintaining high performance while freeing wiring channels.
3Reliability
If FEOL capacitors with thinner dielectrics are used, then capacitance density is high, but they consume valuable front-side area
Solution Approach 1:
Instead of forming capacitors on the front side of the wafer where thin dielectrics enable high capacitance density, the invention inverts the approach by forming deep trench capacitors on the back side. This inversion allows the use of thicker BEOL-compatible dielectrics while achieving comparable or superior capacitance density through the vertical trench structure, eliminating competition for front-side area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces silicon area consumption and enhances capacitance density, addressing the limitations of conventional capacitors by allowing for efficient power supply decoupling without occupying valuable FEOL space and enabling high-k dielectric use without thermal budget constraints.
Implementation Method 1
The method includes forming a through-silicon-via on the substrate... wherein the through-silicon-via connects the deep trench capacitor to the devices
Implementation Method 2
forming a deep trench capacitor in the deep trench... filling the deep trench with a conductive material... forming a buried plate in the substrate, wherein the buried plate contacts the through-silicon-via
Implementation Method 3
depositing a node dielectric layer in the deep trench
Implementation Method 4
The method includes performing an anneal
Data Source
AI summary
A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.