Deep Trench Capacitor Bridge for Low-Impedance Multi-Chip PDN
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Solution Overview
Problem
In power delivery network (PDN) design for multi-chip packages with embedded multi-die interconnect bridges (EMIB), achieving low impedance and high decoupling capacitance density is challenging, especially when the EMIB interface is deep inside the die edge, leading to increased package size and cost, and trade-offs in input/output density and form factor.
Innovation Solution
The introduction of deep trench capacitors (DTC) with conductive fillings and a dielectric layer in a bridge substrate, providing a shorter decoupling capacitance connection between power domains, reducing power delivery network impedance, and increasing decoupling capacitance density compared to traditional metal-insulator-metal capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If package die side capacitor (DSC) design is used to provide decoupling capacitance, then power integrity is improved, but package surface area increases leading to larger form factor and higher costs
Solution Approach 1:
The patent transitions from planar surface-mounted capacitors to three-dimensional deep trench capacitors etched into the package substrate. By utilizing the vertical dimension (depth) rather than only horizontal surface area, the design achieves higher capacitance density (400-800 nF/mm²) while minimizing the footprint on the package surface, thus resolving the contradiction between power integrity and form factor.
Solution Approach 2:
The deep trench capacitors are nested within the package substrate structure itself, with trenches etched into the substrate and filled with conductive material. This nesting approach integrates the capacitor function directly into the substrate volume, eliminating the need for separate surface-mounted capacitor components and reducing overall package area while maintaining decoupling performance.
2Reliability
If package land-side capacitor (LSC) design is used, then decoupling capacitance is provided, but BGA cavity keep-out zone increases leading to reduced I/O density
Solution Approach 1:
By moving capacitor placement from the two-dimensional package surface (LSC design) to the three-dimensional substrate volume (deep trench capacitors), the invention eliminates the need for large BGA cavity keep-out zones. The vertical integration of capacitors into the substrate allows BGA balls to be placed more densely on the surface without interfering with capacitor functionality, thus increasing I/O density while maintaining power integrity.
3Reliability
If traditional metal-insulator-metal capacitors are used, then decoupling capacitance is provided, but capacitance density is limited and package real-estate requirements increase
Solution Approach 1:
The deep trench capacitors nest multiple conductive layers and dielectric materials within vertical trenches etched into the substrate. This nested structure provides significantly higher capacitance per unit area (400-800 nF/mm²) compared to traditional MIM capacitors, as the capacitive elements are stacked vertically rather than arranged horizontally, thus increasing capacitance density without requiring additional package real estate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables improved power integrity with reduced impedance and higher capacitance density, facilitating device miniaturization by minimizing package real-estate requirements and maintaining high performance.
Implementation Method 1
The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each trench of the plurality of trenches may include a conductive filling; a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer
Data Source
AI summary
A device is provided, including a bridge substrate and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each of the plurality of trenches may include a conductive filling; a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer; a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer; and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches.