Deep Trench Capacitor Crystallographic Etching
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Solution Overview
Problem
The challenge in embedded dynamic random access memory (eDRAM) is the reduction in capacitance due to device scaling, which affects performance as the available device area per capacitor decreases, and deep trench capacitor etching becomes less effective with increasing depth, leading to insufficient capacitance for optimal eDRAM performance.
Innovation Solution
A semiconductor structure is created with a doped polycrystalline semiconductor layer, where a deep trench is formed and the exposed vertical surfaces are crystallographically etched to increase the surface area, and a node dielectric and conductive material are deposited to form a capacitor, along with access transistors and moat isolation structures to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling is performed to increase eDRAM density, then device area per capacitor decreases, but capacitance becomes insufficient
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional deep trench structure. By etching vertical trenches into the substrate and forming capacitors within these trenches, the design exploits the vertical dimension to increase capacitance without occupying additional lateral device area. This dimensional transition allows sufficient capacitance to be achieved in scaled-down device footprints.
Solution Approach 2:
The capacitor structure is nested within the deep trench, with the node dielectric and electrodes embedded in the vertical trench space. This nesting approach efficiently utilizes the available three-dimensional space within the trench boundaries, maximizing capacitance within a compact vertical footprint that does not increase the lateral device area.
2Quantity of substance
If deep trench depth is increased to maintain capacitance, then etching effectiveness decreases exponentially
Solution Approach 1:
The patent modifies the etching process parameters and chemistry to maintain effectiveness at increased trench depths. By adjusting etch selectivity, using appropriate etch chemistries, and optimizing process conditions, the manufacturing process can successfully create deep trenches with sufficient capacitance while remaining feasible for production.
3Area of stationary object
If device area per capacitor is reduced for scaling, then capacitance surface area decreases
Solution Approach 1:
The patent resolves this area constraint by moving from a two-dimensional surface area model to a three-dimensional volume model. The deep trench structure provides vertical surface area through the trench walls, allowing sufficient capacitance surface area to be achieved within a reduced lateral footprint. The vertical dimension compensates for the reduced horizontal area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the total exposed surface area of the polycrystalline semiconductor layer within the deep trench, thereby enhancing the capacitance of the eDRAM, addressing the limitations of traditional deep trench capacitors and maintaining performance even at smaller device sizes.
Implementation Method 1
Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench
Data Source
AI summary
A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.