Deep Trench Capacitor Structure for High-Capacitance Small Footprints
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to create high-capacitance capacitors with a small device footprint to address the need for efficient power delivery and noise suppression in advanced packaging technologies like Chip-on-Wafer-on-Substrate (CoWoS) and System on Integrated Chips (SoIC), which are sensitive to fluctuating supply voltages due to increased current densities and larger current transients.
Innovation Solution
The development of a deep-trench-capacitor (DTC) structure formed by etching deep trenches in a semiconductor substrate, filling them with alternating layers of metallic electrodes and dielectric materials, and connecting them with metal vias to achieve high capacitance in a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional capacitor fabrication methods are used, then manufacturing process is simple, but device area occupied is large
Solution Approach 1:
The patent transitions from planar (2D) capacitor structures to vertical (3D) deep trench structures. By etching trenches that extend vertically into the substrate and filling them with alternating metallic electrode and dielectric layers, the capacitor achieves high capacitance within a minimal footprint area, effectively utilizing the third dimension (depth) to increase functional density without expanding the device area.
Solution Approach 2:
The capacitor structure employs nested alternating layers of metallic electrodes and dielectric materials within the deep trench. Multiple electrode-dielectric pairs are stacked vertically one inside another, similar to nested dolls, where each layer contributes to the overall capacitance while maintaining a compact structure that fits within the trench volume.
2Area of stationary object
If capacitor size is reduced to save area, then device footprint decreases, but capacitance value drops
Solution Approach 1:
The invention compensates for reduced planar area by extending the capacitor structure vertically into deep trenches. The increased depth provides additional volume for stacking multiple electrode-dielectric layers, thereby maintaining or increasing total capacitance despite the reduced footprint area.
Solution Approach 2:
The capacitor utilizes composite structures with alternating layers of different materials - metallic electrodes (such as tungsten or copper) and dielectric materials (such as silicon nitride or silicon oxide). This composite layering within the deep trench maximizes the capacitance density by optimizing the electrical properties of each material layer while maintaining a compact overall structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DTC structure provides high capacitance with reduced resistance and improved manufacturing yield, enhancing power integrity and noise suppression in semiconductor packages by integrating capacitors efficiently within the limited space.
Implementation Method 1
forming first-type deep trenches and second-type deep trenches in a substrate
Implementation Method 2
depositing a first metallic layer over the substrate and into the first-type deep trenches and second-type deep trenches
Data Source
AI summary
A method includes forming first-type deep trenches and second-type deep trenches in a substrate, in which the first-type deep trenches have a first lengthwise direction along a first direction and the second-type deep trenches have a second lengthwise direction along a second direction; forming a capacitor structure over the substrate and in the first-type deep trenches and the second-type deep trenches, in which the capacitor structure includes a first metallic electrode layer, a node dielectric layer over the first metallic electrode layer, and a second metallic electrode layer over the node dielectric layer; and forming a first metal via over the capacitor structure and in contact with the second metallic electrode layer of the capacitor structure, in which a length of the first metal via is greater than a width of the first metal via from a top view.