Deep Trench Capacitor Layout for Power Integrity and Low Warpage
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Solution Overview
Problem
The miniaturization of devices on modern integrated circuits has led to increased sensitivity to fluctuating supply voltages, exacerbating power integrity challenges, as decoupling capacitors are often physically located in close proximity to the circuit to reduce parasitic inductances and resistances, necessitating high-density capacitors that can be easily integrated on the IC.
Innovation Solution
The implementation of a deep trench capacitor (DTC) region in semiconductor packages, comprising a substrate with trenches filled with conductive and dielectric layers, allowing for high-density capacitors that can be flexibly organized to meet specific capacitance requirements and reduce warpage through perpendicular trench orientations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor designs are used in advanced packaging, then manufacturing simplicity is maintained, but capacitance density remains insufficient to meet power delivery requirements
Solution Approach 1:
The patent transitions from planar capacitor designs to three-dimensional deep trench structures, extending capacitance generation vertically into the substrate. Multiple conductive layers are stacked at different depths within the same footprint area, achieving capacitance densities exceeding 300 nF/mm2 by utilizing the third dimension (depth) rather than only horizontal expansion.
Solution Approach 2:
The capacitor structure employs nested concentric conductive layers within cylindrical or rectangular trenches. Inner conductive layers are surrounded by outer layers, with dielectric materials filling the spaces between them. This nested configuration maximizes the surface area for capacitance formation within a compact volume, enabling high capacitance density without proportionally increasing footprint area.
2Reliability
If capacitor density is increased to reduce impedance, then power integrity improves, but noise and warpage issues arise
Solution Approach 1:
The capacitor array is strategically positioned in specific regions of the substrate, with varying densities and configurations tailored to local power delivery requirements. High-density capacitor banks are placed near high-current consuming areas, while lower-density regions are used where less power conditioning is needed. This localized optimization achieves power integrity improvement without uniformly increasing noise and warpage across the entire package.
Solution Approach 2:
The capacitor structures employ asymmetric configurations including non-uniform trench depths, varied conductive layer thicknesses, and irregular spacing patterns. These asymmetric designs allow for stress distribution optimization and thermal management, reducing warpage while maintaining high capacitance density. The asymmetric layouts also enable better noise isolation by positioning high-frequency switching capacitors away from sensitive analog regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DTC region provides high capacitance density and flexibility in capacitor design, effectively reducing impedance and voltage drop while minimizing warpage, thus enhancing power integrity and performance in advanced packaging technologies like CoWoS and SoIC.
Implementation Method 1
each DTC unit includes a trench extending downwardly from a top surface of the substrate; a first conductive layer disposed in the trench; a second conductive layer disposed in the trench; and a dielectric layer sandwiched by the first conductive layer and the second conductive layer
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a substrate and a deep trench capacitor (DTC) region formed in the substrate. The DTC region includes a plurality of DTC units, and each DTC unit includes: a trench extending downwardly from a top surface of the substrate; a first conductive layer disposed in the trench; a second conductive layer disposed in the trench; and a dielectric layer sandwiched by the first conductive layer and the second conductive layer. Each DTC unit is elongated, and a first group of the plurality of DTC units extend horizontally in a first direction, whereas a second group of the plurality of the DTC units extend horizontally in a second direction.