Deep Trench Capacitor With Programmable Leakage
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Solution Overview
Problem
Current memory devices, such as DRAM, require periodic refreshing due to capacitor leakage, while SRAM induces stand-by power consumption even when not accessed, necessitating a non-volatile memory device that minimizes power consumption in stand-by mode.
Innovation Solution
A non-volatile memory device with a programmable leakage level is formed using a deep trench capacitor with a metal-insulator-metal stack and a set of switching devices, allowing for three states based on input signals: electrical short to positive or negative power supply, or isolation from both, achieved by forming a thinner node dielectric layer for the non-volatile memory device compared to DRAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in DRAM for charge storage, then data can be stored, but periodic refreshing is required due to leakage
Solution Approach 1:
The patent changes the electrical parameter of the dielectric layer by forming regions with different thicknesses (thinner and thicker portions) to create variable leakage characteristics. This allows the capacitor to operate in different states (retention mode and refresh mode) by controlling the leakage current through selective thinning of the dielectric layer in specific regions.
2Reliability
If SRAM is used for non-volatile memory, then periodic refreshing is not required, but stand-by power consumption occurs even when not accessed
Solution Approach 1:
The patent makes the capacitor's leakage characteristic dynamic and controllable by creating a dielectric layer with spatially varying thickness. The system can transition between different operational states (high leakage for refresh, low leakage for retention) based on control signals, enabling the memory to adapt its power consumption and retention characteristics as needed.
3Adaptability or versatility
If a deep trench capacitor with variable dielectric thickness is formed, then programmable leakage levels are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the dielectric layer into distinct thickness regions (thinner and thicker portions) within the same capacitor structure. This segmentation is achieved through selective etching or deposition processes that create different dielectric thicknesses in different spatial regions, enabling programmable leakage control without requiring entirely separate device structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a semiconductor structure with reduced stand-by power consumption by allowing the non-volatile memory device to maintain data without periodic refreshing and minimizing power usage when not accessed, concurrently with DRAM device manufacturing processes.
Implementation Method 1
a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage
Data Source
AI summary
A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.