Deep Trench Capacitor Structure Without Planarization
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Solution Overview
Problem
Conventional planar capacitors struggle to meet the increasing capacitance demands of artificial intelligence (AI) and high-performance computing (HPC) while accommodating miniaturization needs, necessitating an improved structure and fabrication method for deep trench capacitors.
Innovation Solution
A semiconductor device with a trench capacitor structure featuring a bottom electrode layer, insulating layer, and top electrode layer, where a dielectric layer with a recessed portion is formed within the trench, and a method that includes forming a trench in a substrate, depositing these layers without a planarization process to enhance capacitance and reduce production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar capacitor structures are used, then the fabrication process is simple, but the capacitance value is insufficient for AI and HPC applications
Solution Approach 1:
The patent transitions from planar (2D) capacitor structures to deep trench (3D) capacitor structures by etching vertical trenches into the substrate. This dimensional change allows the capacitor electrodes to extend vertically, significantly increasing the effective capacitance area without increasing the planar footprint, thereby meeting the high capacitance demands of AI and HPC applications while maintaining fabrication feasibility
2Quantity of substance
If deep trench capacitor structures are adopted to increase capacitance, then the capacitance value increases, but the risk of substrate fracture increases
Solution Approach 1:
The patent applies local quality by forming a stress relief structure (such as a relaxed nitride layer or void space) at specific locations within the deep trench capacitor structure. This localized feature relieves mechanical stress concentrated in the substrate walls caused by the deep trench etching process, preventing substrate fracture while preserving the high capacitance benefits of the deep trench configuration
Solution Approach 2:
The patent incorporates stress relief structures during the fabrication process as a preventive measure. These structures act as cushioning elements that absorb or redistribute mechanical stress before it can propagate through the substrate and cause fracture, thereby ensuring substrate reliability throughout subsequent processing and device operation
3Manufacturing precision
If planarization process is performed to improve surface flatness, then the surface flatness increases, but the fabrication complexity and production cost increase
Solution Approach 1:
The patent extracts or eliminates the planarization process from the fabrication sequence by designing the deep trench capacitor structure and surrounding dielectric layers to inherently provide sufficient surface flatness. This is achieved through careful structural design where the trench walls and overlying layers self-align without requiring additional mechanical or chemical-mechanical polishing steps, thereby reducing fabrication complexity and production cost while maintaining the necessary manufacturing precision
Data Source
AI summary
A semiconductor device includes a trench, a capacitor structure and a dielectric layer. The trench is formed in a substrate. The capacitor structure is disposed in the trench. The capacitor structure includes a bottom electrode layer, an insulating layer and a top electrode layer. The bottom electrode layer is disposed in the trench and on a top surface of the substrate. The insulating layer is disposed on the bottom electrode layer. The top electrode layer is disposed on the insulating layer. The dielectric layer is disposed on the top electrode layer. A portion of the dielectric layer is filled in the trench, and the dielectric layer includes a recessed portion disposed above the trench.