Deep Trench Capacitor for SOI CMOS Soft Error Immunity
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Solution Overview
Problem
Existing methods to reduce soft error rates (SER) in semiconductor circuits, such as those in memory devices, often increase manufacturing costs and add area or delay due to the need for additional devices or capacitance, which complicates the mitigation of noise-induced errors.
Innovation Solution
Incorporating a deep trench capacitor electrically connected to the body/channel region of semiconductor devices within a CMOS structure, which increases the critical charge (Qcrit) and reduces the soft error rate by adding capacitance without substantial area or delay penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional devices or capacitance are added to harden the circuit against soft errors, then the critical charge (Qcrit) increases and soft error rate decreases, but the manufacturing cost increases substantially
Solution Approach 1:
The deep trench capacitor is merged with the existing semiconductor device structure, sharing the same substrate and being formed in the same fabrication process flow. The capacitor utilizes the same n-well region and shares process steps such as oxidation, deposition, and etching with the transistor fabrication, thereby avoiding substantial additional manufacturing costs while increasing Qcrit to reduce soft error rate
Solution Approach 2:
The n-well region serves multiple functions: it acts as the body region for the n-channel transistor and simultaneously serves as one of the electrodes for the deep trench capacitor. This multi-functionality allows the structure to provide both transistor operation and soft error mitigation without requiring entirely separate dedicated structures, reducing manufacturing complexity and cost
2Reliability
If additional devices or capacitance are added to harden the circuit against soft errors, then the critical charge (Qcrit) increases and soft error rate decreases, but the device area increases
Solution Approach 1:
The deep trench capacitor is nested within the existing device footprint by forming the capacitor trench in the substrate beneath and adjacent to the transistor channel. The capacitor structure is embedded in the same area where the transistor is formed, utilizing vertical space and shared regions (such as the n-well) rather than requiring additional lateral area, thus reducing the overall device area compared to separate capacitor implementations
3Reliability
If additional devices or capacitance are added to harden the circuit against soft errors, then the critical charge (Qcrit) increases and soft error rate decreases, but the device delay increases
Solution Approach 1:
The deep trench capacitor is formed during the preliminary stages of the fabrication process, before the transistor gate and source/drain regions are fully formed. The capacitor structure is prepared in advance using early process steps such as trench formation, insulation deposition, and initial doping, allowing the soft error mitigation functionality to be built in without interfering with subsequent critical transistor formation steps, thereby minimizing impact on device speed and delay
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deep trench capacitor effectively stabilizes the threshold voltage and reduces current transmission across semiconductor devices, thereby lowering the soft error rate while minimizing manufacturing costs.
Implementation Method 1
a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device
Data Source
AI summary
A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.