Deep Trench Capacitor Stack for High Density IC Integration
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Solution Overview
Problem
Conventional capacitors on integrated circuits face challenges in achieving high density and efficient noise reduction due to parasitic inductances and resistances associated with interconnects, necessitating the development of a high-density capacitor design that can be easily integrated into IC technology.
Innovation Solution
The solution involves stacking two or more deep trench capacitors in parallel, with each capacitor having conductive plates separated by dielectric layers, increasing capacitance density by optimizing trench geometry and dielectric material usage, and coupling them through an interconnect structure to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor designs are used, then the capacitor can be easily manufactured, but the capacitance density is insufficient and interconnect noise cannot be effectively reduced
Solution Approach 1:
The patent transitions from planar capacitor geometry to vertical deep trench geometry, utilizing the third dimension (depth) to increase capacitance density. The deep trench capacitors extend vertically into the substrate, providing significantly larger capacitor plate area within the same footprint, thereby achieving high capacitance density without proportionally increasing device complexity
Solution Approach 2:
The patent implements stacked capacitor structures where multiple deep trench capacitors are nested vertically, with upper capacitors positioned above lower capacitors. This nesting approach allows multiple capacitor elements to occupy the same horizontal footprint, dramatically increasing capacitance density while maintaining a compact, integrated structure that does not linearly increase manufacturing complexity
2Reliability
If capacitor density is increased by placing capacitors closer to circuits, then parasitic inductances and resistances are reduced, but the capacitor layout becomes more complex
Solution Approach 1:
By moving capacitor plates vertically into deep trenches rather than spreading them out horizontally, the patent achieves close coupling with circuits in the vertical dimension. This reduces the horizontal distance between capacitor and circuit, minimizing parasitic inductances and resistances while maintaining a regular, manageable layout pattern
Solution Approach 2:
The patent divides the capacitor structure into multiple discrete deep trench elements that can be independently formed and positioned. Each trench is a separate, well-defined structure that can be precisely located close to circuit elements, reducing layout complexity compared to large-area planar capacitors while achieving the same noise reduction effect
3Quantity of substance
If deep trench capacitors are stacked in parallel, then capacitance density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps where mandrels are formed first, followed by trench etching. These preliminary structures serve as templates that guide subsequent dielectric deposition and conductive plate formation, ensuring precise alignment of stacked capacitors without requiring extreme precision in each individual step
Solution Approach 2:
The stacked capacitor structure is built through sequential nesting of layers - dielectric materials are deposited conformally within trenches, followed by conductive plates, then repeated for upper capacitors. Each layer nests within the previous structure, with self-aligning features that reduce the cumulative impact of manufacturing variations and lower precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-density capacitor layout that effectively reduces interconnect noise by increasing capacitance density, improving noise reduction capabilities compared to conventional solutions.
Implementation Method 1
each capacitor having conductive plates separated by dielectric layers
Implementation Method 2
A first dielectric layer is formed in the plurality of trenches and a first conductive layer is formed in the plurality of trenches over the first dielectric layer
Data Source
AI summary
Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.