Deep Trench Capacitor Parallel Stacking for High Density
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Solution Overview
Problem
Conventional capacitors in integrated circuits face challenges in achieving high density and efficient noise reduction due to parasitic inductances and resistances associated with interconnects, necessitating the development of a high-density capacitor solution that can be easily integrated into IC technology.
Innovation Solution
The solution involves stacking multiple deep trench capacitors in parallel, with each capacitor comprising conductive plates separated by dielectric layers, and an interconnect structure that couples these capacitors to increase capacitance density, utilizing a semiconductor substrate with highly doped regions and trench structures to enhance capacitance through increased plate area and reduced distance between plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor designs are used, then manufacturing processes are simpler, but capacitance density is insufficient and noise reduction effectiveness is limited
Solution Approach 1:
The patent transitions from planar capacitor designs to three-dimensional deep trench structures, utilizing vertical space to increase capacitance density. Multiple capacitor plates are stacked vertically within deep trenches etched into the substrate, effectively using the third dimension (depth) to pack more capacitance into a smaller footprint area.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor plates and dielectric layers are stacked within each other inside deep trenches. Each trench contains a series of nested capacitive elements, with conductive plates separated by dielectric layers, creating a compact nested arrangement that maximizes capacitance within the available volume.
2Reliability
If capacitors are placed close to the circuit, then parasitic inductances and resistances are reduced, but achieving high density becomes more difficult
Solution Approach 1:
By using vertical deep trench structures instead of planar layouts, the patent achieves high capacitance density without requiring large horizontal spacing from circuits. The vertical stacking allows capacitors to be placed close to circuit elements while maintaining high capacitance values through the increased effective plate area in the vertical dimension.
3Quantity of substance
If deep trench structures are used, then capacitance density increases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming deep trenches, depositing dielectric layers, forming conductive plates, and creating interconnect structures. This segmentation allows each step to be optimized independently and enables the use of standard semiconductor manufacturing techniques adapted for deep trench applications.
Solution Approach 2:
The patent employs preliminary actions in the manufacturing process, such as pre-forming deep trenches before depositing capacitor structures, and using sacrificial layers that are removed after serving their purpose. These preliminary steps simplify subsequent processing and enable the formation of complex three-dimensional capacitor structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-density capacitor layout that effectively increases capacitance density, reduces noise interference, and streamlines manufacturing processes by eliminating certain steps like chemical mechanical polishing and photolithography, thereby improving integration and performance.
Implementation Method 1
a first trench capacitor, a second trench capacitor and an interconnect structure. The first trench capacitor comprises a first capacitor plate disposed in a plurality of trenches in a semiconductor substrate, and a second capacitor plate disposed in the plurality of trenches and separated from the first capacitor plate by a first dielectric
Implementation Method 2
separated from the first capacitor plate by a first dielectric along bottom and sidewall surfaces of the plurality of trenches
Data Source
AI summary
Some embodiments relate to high density capacitor structures. Some embodiments include a first trench capacitor, a second trench capacitor and an interconnect structure. The first trench capacitor includes a first capacitor plate disposed in a plurality of trenches in a semiconductor substrate, and a second capacitor plate disposed in the plurality of trenches and separated from the first capacitor plate by a first capacitor dielectric along bottom and sidewall surfaces of the plurality of trenches. The second trench capacitor is disposed over the first trench capacitor. The second trench capacitor includes the second capacitor plate, and a third capacitor plate disposed in the plurality of trenches and separated from the second capacitor plate by a second capacitor dielectric. The interconnect structure connects the first capacitor plate and the third capacitor plate such that the first and second trench capacitors are in parallel.