Deep Trench Isolation Structure With Coplanar Gap-Fill Planarization
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Solution Overview
Problem
The implementation of deep trench isolation in semiconductor devices is complicated due to the need for multiple masks and is further complicated by variations in gate structure height, leading to increased process complexity.
Innovation Solution
A semiconductor device design featuring a deep trench isolation structure with a planarized gap-fill insulating layer coplanar with a hard mask, a capping insulating layer, and sidewall insulating layers, along with contact plugs penetrating the hard mask and gap-fill insulating layer, to simplify the manufacturing process and reduce chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench isolation structure is implemented, then electrical isolation between semiconductor devices is improved, but manufacturing process complexity increases due to multiple masks and complicated filling processes
Solution Approach 1:
The patent divides the trench isolation formation into distinct segments: shallow trench isolation layer first, then deep trench isolation extending below it. This segmentation allows each trench type to be formed and filled independently, simplifying the overall manufacturing process while maintaining effective electrical isolation between devices.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming the deep trench isolation to extend below the shallow trench isolation layer. This vertical extension provides additional isolation depth without requiring additional lateral mask patterns, thereby improving electrical isolation while avoiding increased process complexity from multiple masks.
2Adaptability or versatility
If gate structure height varies, then device functionality is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent creates a planarized gap-fill insulating layer that provides a flat, equipotential surface across regions with varying gate structure heights. This planarization layer compensates for height differences, allowing subsequent processing steps to be performed uniformly without requiring complex height-matching processes for each gate structure.
Solution Approach 2:
The patent introduces a gap-fill insulating layer as an intermediary element between the substrate and upper processing layers. This intermediary layer fills the spaces around gate structures of varying heights, providing a uniform reference plane that simplifies subsequent manufacturing steps while accommodating gate height variations.
3Reliability
If deep trench isolation with multiple masks is used, then electrical isolation is improved, but chip area increases
Solution Approach 1:
The patent merges the shallow trench isolation and deep trench isolation into a single integrated isolation structure. The shallow trench provides surface-level isolation while the deep trench extends below, and both are formed using the same mask pattern, eliminating the need for additional masks and reducing chip area.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.