Deep Trench High-K Capacitor Layout for Higher Capacitance Density
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Solution Overview
Problem
Integrating capacitors into integrated circuits is challenging due to the limited available area, which restricts the achievable capacitance per unit area.
Innovation Solution
The integration of a dielectric layer over a semiconductor substrate with trenches containing a conductive trench electrode and a dielectric liner, capped by a cap dielectric layer, enhances capacitance by utilizing high-K dielectric materials and conformal deposition techniques like ALD to form deep trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar capacitor structures are used, then the device occupies minimal area, but the capacitance per unit area is insufficient
Solution Approach 1:
The patent transitions from a planar (2D) capacitor structure to a three-dimensional trench structure. Deep trenches are etched into the substrate, and the capacitor electrodes and dielectric layers are formed within these trenches, utilizing the vertical dimension to increase capacitance density. This dimensional transition allows achieving 54 fF/μm², which is 40 times greater than planar capacitors.
Solution Approach 2:
The patent implements a nested structure where multiple dielectric layers (first dielectric layer, second dielectric layer) and electrodes (first trench electrode, second trench electrode) are sequentially formed within the trenches. The cap dielectric layer is deposited over the gate electrode, creating a nested configuration that maximizes the use of available space and increases capacitance per unit area.
2Quantity of substance
If deep trenches are formed to increase capacitance, then capacitance per unit area increases, but contamination and resistance effects worsen
Solution Approach 1:
The patent applies a dielectric liner to the trench walls before forming the capacitor electrodes and dielectric layers. This preliminary action prevents contamination during subsequent processing steps and reduces resistance effects by providing a clean, controlled interface between the trench structure and the deposited materials. The liner is formed prior to electrode deposition, establishing a protective barrier in advance.
Solution Approach 2:
The dielectric liner acts as an intermediary layer between the trench structure and the capacitor electrodes/dielectric layers. It mediates the interaction by preventing direct contact between potentially contaminating materials and the trench walls, while also providing electrical insulation and reducing resistance effects at the interfaces.
3Quantity of substance
If high-K dielectric materials are used, then capacitance per unit area increases significantly, but manufacturing complexity increases
Solution Approach 1:
The patent divides the dielectric structure into multiple segments: a first dielectric layer, a second dielectric layer, and a cap dielectric layer. Each layer can be formed using different materials with appropriate K values, allowing optimization of capacitance while managing manufacturing complexity. The segmented structure enables selective deposition and processing of each layer.
Solution Approach 2:
The patent employs composite dielectric structures combining multiple materials with different dielectric properties. The first and second dielectric layers may use different high-K materials, and the cap dielectric layer provides additional functionality. This composite approach achieves high capacitance per unit area (54 fF/μm²) while allowing flexibility in manufacturing process design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases capacitance per unit area, achieving up to 54 fF/μm2, which is three times greater than baseline deep trench capacitors and 40 times that of planar capacitors, while minimizing contamination and resistance effects.
Implementation Method 1
A dielectric liner is deposited on a sidewall of the trench
Implementation Method 2
A cap dielectric layer is formed that touches a top surface of the conductive material and extends over the gate electrode
Data Source
AI summary
Described examples include an integrated circuit including a dielectric layer located over a top surface of a semiconductor substrate and extending over a gate electrode. A trench extends from a top surface of the dielectric layer into the substrate. A conductive trench electrode is within the trench, and a dielectric liner is between the trench electrode and the semiconductor substrate. A cap dielectric layer is located on the conductive trench electrode and on the dielectric layer, and extends over the gate electrode.