Deep Trench Isolation Profile for HV-LV Semiconductor Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in integrating high-voltage and FinFET devices due to issues like current leakage and breakdown voltage control as device scaling decreases, necessitating improved fabrication methods for deep trench isolation.
Innovation Solution
A semiconductor device fabrication method involving a substrate divided into high and low voltage regions, with specific deep trench isolation structures formed using multiple etching processes to create unique sidewall profiles and filled with insulating layers, ensuring effective isolation and transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench isolation is formed in high voltage region, then breakdown voltage control is improved, but current leakage occurs
Solution Approach 1:
The patent applies local quality by forming different trench depth profiles in different regions: deep trenches in high voltage regions for breakdown control, and shallow trenches in low voltage regions to prevent leakage. The trench sidewalls are also given different slopes in different regions, with steeper slopes in low voltage areas to minimize leakage paths while maintaining adequate isolation in high voltage areas.
Solution Approach 2:
The patent changes geometric parameters of the trenches including depth, sidewall slope, and cross-sectional shape to optimize performance. By adjusting the trench depth from shallow in low voltage regions to deep in high voltage regions, and modifying sidewall slopes, the patent achieves both breakdown voltage control and leakage prevention through parameter optimization.
2Reliability
If three-dimensional FinFET structure is used, then channel control is improved, but integration with high-voltage devices becomes difficult
Solution Approach 1:
The patent applies local quality by creating region-specific structures: FinFETs with their three-dimensional channel structures are placed in low voltage regions where they provide superior channel control, while high voltage devices are positioned in separate regions with appropriate isolation. The deep trench isolation structures are strategically located at interfaces between different voltage regions to enable co-integration while maintaining electrical isolation.
Solution Approach 2:
The patent segments the semiconductor device into distinct high voltage and low voltage regions separated by deep trench isolations. This segmentation allows FinFETs to operate in their optimal low voltage environment with excellent channel control, while high voltage devices are isolated in separate regions, reducing integration complexity by preventing electrical interference between the two device types.
3Productivity
If device scaling is reduced, then integration density is improved, but current leakage and breakdown voltage control deteriorate
Solution Approach 1:
The patent changes the scaling parameters differently for different device regions. While overall device dimensions are scaled down to increase integration density, the trench depth, width, and spacing are adjusted to maintain adequate isolation. The trench sidewall slopes are optimized to prevent leakage even as dimensions are reduced, allowing continued breakdown voltage control despite aggressive scaling.
Solution Approach 2:
The patent applies local quality by maintaining larger trench dimensions and more conservative spacing in high voltage regions even as overall device scaling proceeds. This localized approach to isolation structure sizing allows the device to achieve high integration density through scaling while preventing leakage and maintaining breakdown voltage control in the high voltage regions through appropriately sized isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the performance of high-voltage and FinFET devices by improving breakdown voltage control and reducing current leakage through precise deep trench isolation, allowing for efficient integration of high-voltage and low-voltage transistors on a single chip.
Implementation Method 1
a first etching process is performed. The first etching process includes removing entirely at least one of the fin structures and etching the substrate within the high voltage region to form a first trench within the high voltage region
Data Source
AI summary
A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.