Deep Trench Insulation Layout for Compact 150V Semiconductor Isolation
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Solution Overview
Problem
Current Deep Trench Insulation (DTI) technology for high voltage semiconductor devices is costly and inefficient due to the need for multiple etching steps and variability in manufacturing, which can lead to reduced oxide lining and compromised voltage breakdown, especially when attempting to integrate multiple DTIs with different dimensions in a single chip.
Innovation Solution
A manufacturing process that simultaneously forms first and second trenches with varying depths and widths, where the first trench has a greater depth and width than the second, allowing for the formation of insulation walls and a solid insulating region, with the second trench being completely filled with a conductive material to create a second insulation structure, reducing overall device area and maintaining voltage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple DTIs with different dimensions are integrated in a single chip using conventional methods, then device functionality is improved, but manufacturing complexity and cost increase due to multiple etching steps
Solution Approach 1:
The patent merges multiple etching operations into a single etching step by using a common etch mask that defines multiple trench patterns simultaneously. This allows DTIs of different dimensions to be formed in one manufacturing step rather than requiring separate etching steps for each trench, thereby reducing process complexity while maintaining the ability to integrate multiple DTIs with varying dimensions on a single chip.
2Adaptability or versatility
If multiple DTIs with different dimensions are integrated in a single chip, then device functionality is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple trench formation operations into a single etching step using a common etch mask, which directly reduces manufacturing cost by eliminating redundant process steps. This approach maintains full adaptability for creating DTIs of different dimensions while making the manufacturing process more cost-effective through process consolidation.
3Manufacturing precision
If conventional multi-step etching is used for DTI formation, then manufacturing precision can be maintained, but productivity decreases due to multiple processing steps
Solution Approach 1:
The patent merges multiple etching steps into one simultaneous etching operation using a common etch mask that defines all trench patterns at once. This consolidation maintains manufacturing precision through consistent etching parameters applied across all trenches while significantly improving productivity by reducing the total number of processing steps and cycle time.
4Reliability
If DTI dimensions vary to optimize device performance, then voltage capabilities are improved, but oxide lining quality deteriorates due to manufacturing variability
Solution Approach 1:
The patent uses a single etching step with a common etch mask to form all DTI trenches simultaneously, ensuring that oxide lining is deposited uniformly across all trenches under identical process conditions. This approach maintains consistent oxide lining quality despite variations in trench dimensions, thereby preserving voltage breakdown capability while allowing optimization of different DTI sizes for specific device performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the minimum distance between insulation and conductive regions, allowing for a 40% area reduction in high voltage devices while maintaining voltage capabilities up to 150V, and is manufactured in a single step at standard costs, enhancing the efficiency and cost-effectiveness of semiconductor device production.
Implementation Method 1
simultaneously forming insulation walls on sidewalls of the first trench and a solid insulating region in the second trench
Data Source
AI summary
A body of semiconductor material has a surface and accommodates an active area, conductive regions, a first deep insulation structure extending in the active area from the surface of the body in a first trench, and a second deep insulation structure extending in the active area from the surface of the body in a second trench and surrounding the conductive regions. The first deep insulation structure has insulation walls surrounding a conductive filling portion. The second deep insulation structure has a solid insulating region filling the second trench. The first deep insulation region has a first width and a first depth and the second deep insulation structure has a second width and a second depth. The second width is smaller than the first width and the second depth is smaller than the first depth.