Deep Trench Interposer Capacitor for ASIC Voltage Droop
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Solution Overview
Problem
Integrated circuit packages face voltage droop issues due to high current draws and rapid changes in current, which cause power supply voltage fluctuations, especially at intermediate frequency ranges, as existing capacitors on PCBs or etched into the ICs do not adequately mitigate inductive, resistive, and resonant effects.
Innovation Solution
Embedding deep trench capacitors or other three-dimensional structures within the interposer, close to the integrated circuit, to provide additional capacitance and mechanical stability, filling unoccupied space and using similar fabrication techniques to the ICs and memory circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are placed on the power supply lines in the vicinity of the processor, then voltage smoothing is improved, but space within the processor package is consumed
Solution Approach 1:
The capacitor structure transitions from a planar two-dimensional layout to a three-dimensional deep trench configuration. Conductive plates are stacked vertically with dielectric layers between them, extending in the depth dimension rather than only spreading horizontally. This vertical stacking enables high capacitance values (exceeding 10uF) while occupying minimal surface area on the interposer, effectively resolving the space constraint while maintaining voltage smoothing capability.
2Area of stationary object
If existing capacitors are used on PCBs or etched into ICs, then space is saved, but inductive, resistive, and resonant effects are not adequately mitigated
Solution Approach 1:
The capacitor is positioned locally within the interposer in close proximity to the integrated circuit die, rather than being placed remotely on the PCB. This local placement minimizes the length of power supply traces, reducing inductive and resistive effects. The deep trench structure with multiple conductive plates and dielectric layers provides high capacitance density at the critical location near the processor, effectively mitigating voltage droop and power supply noise.
3Reliability
If deep trench capacitors are embedded in the interposer, then capacitance density and mechanical stability are improved, but fabrication complexity increases
Solution Approach 1:
The deep trench capacitor structure is integrated into the interposer fabrication process alongside the integrated circuit and memory circuit manufacturing. The same semiconductor fabrication techniques—such as depositing conductive layers, forming dielectric layers, and etching trenches—are used to create both the functional circuits and the capacitor structures. This multi-functional approach allows the interposer to serve both as a mounting substrate and as a host for high-capacitance decoupling elements, achieving capacitance density exceeding 10uF without requiring separate fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces voltage droop by providing higher capacitance density and mechanical stability, maintaining steady power supply voltages and preventing bit errors and transistor damage, with capacitance exceeding 10uF and improving thermal conductivity.
Implementation Method 1
The capacitor includes an oxide layer electrically isolating the capacitor from the interposer
Implementation Method 2
Embedding deep trench capacitors or other three-dimensional structures within the interposer, close to the integrated circuit, to provide additional capacitance
Data Source
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AI summary
A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, a integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.